- 您现在的位置：买卖IC网 > PDF目录199494 > TSPC106AVGS66CG (E2V TECHNOLOGIES PLC) PCI BUS CONTROLLER, CBGA303 PDF资料下载
参数资料
| 型号： | TSPC106AVGS66CG |
| 厂商： | E2V TECHNOLOGIES PLC |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, CBGA303 |
| 封装： | 21 X 25 MM, 3.84 MM HEIGHT, 1.27 MM PITCH, CICGA-303 |
| 文件页数： | 8/41页 |
| 文件大小： | 581K |
| 代理商： | TSPC106AVGS66CG |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页
16
TSPC106A
2102C–HIREL–01/05
PCI Interface Signals
Table 7 lists the PCI interface signals and provides a brief description of their functions.
Note that the bits in Table 7 are referenced in little-endian format.
The PCI specification defines a sideband signal as any signal, not part of the PCI speci-
fication, that connects two or more PCI-compliant agent, and has meaning only to those
agents. The TSPC106 impl em ents four PCI sideband signals -FLSHREQ ,
ISA_MASTER, MEMACK and PIRQ.
Table 7. PCI Interface Signals
Signal
Signal Name
Number of
Pins
I/O
Signal Description
AD[31:0]
Address/data
32
I/O
Represents the physical address during the address phase of a
transaction. During the data phase(s) of a PCI transaction, AD[31:0]
contain data. AD[7:0] define the least significant byte and AD[31:24]
the most significant byte.
C/BE[3:0]
Command/byte
enable
4
O
During the address phase, C/BE[3:0] define the PCI bus command.
During the data phase, C/BE[3:0] are used as byte enables. Byte
enables determine which byte lanes carry meaningful data. C/BE0
applies to the least significant byte.
I
During the address phase, C/BE[3:0] indicates the PCI bus command
that another master is sending. During the data phase C/BE[3:0]
indicate which byte lanes are valid.
DEVSEL
Device select
1
O
Indicates that the TSPC106 has decoded the address and is the target
of the current access.
I
Indicates that some PCI agent (other than the TSPC106) has decoded
its address as the target of the current access.
FLSHREQ
Flush request
1
I
Indicates that a device needs to have the TSPC106 flush all of its
current operations.
FRAME
Frame
1
O
Indicates that the TSPC106, acting as a PCI master, is initiating a bus
transaction.
I
Indicates that another PCI master is initiating a bus transaction.
GNT
PCI bus grant
1
I
Indicates that the TSPC106 has been granted control of the PCI bus.
Note that GNT is a point-to-point signal. Every master has its own GNT
SIGNAL.
IRDY
Initializer ready
1
O
Indicates that the TSPC106, acting as a PCI master, can complete the
current data phase of a PCI transaction. During a write, the TSPC106
asserts IRDY to indicate that valid data is present on AD[31:0]. During
a read, the TSPC106 asserts IRDY to indicate that it is prepared to
accept data.
I
Indicates another PCI master is able to complete the current data
phase of the transaction.
ISA_
MASTER
ISA master
1
I
Indicates that an ISA master is requesting system memory.
LOCK
Lock
1
I
Indicates that a master is requesting exclusive access to memory,
which may require multiple transactions to complete.
MEMACK
Memory
acknowledge
1
O
Indicates that the TSPC106 has flushed all of its current operations
and has blocked all 60x transfers except snoop copy-back operations.
The TSPC106 asserts MEMACK in response to assertion of
FLSHREQ after the flush is complete.
相关PDF资料 |
PDF描述 |
|---|---|
| TSPC106AMGSU66CG | PCI BUS CONTROLLER, CBGA303 |
| TSPC603RMAB/Q6LC | 32-BIT, 166 MHz, RISC PROCESSOR, CQFP240 |
| TSPC860MHVGB/Q40B | 32-BIT, 40 MHz, MICROPROCESSOR, CBGA357 |
| TSPC860MHMZPB/Q40B | 32-BIT, 40 MHz, MICROPROCESSOR, PBGA357 |
| TS(X)PC860MHMZPU40B | 32-BIT, 40 MHz, MICROPROCESSOR, PBGA357 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TSPC106AVGS83CE | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MEMORY CONTROLLER |
| TSPC106AVGS83CG | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MEMORY CONTROLLER |
| TSPC106AVGSU/T66CE | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MEMORY CONTROLLER |
| TSPC106AVGSU/T66CG | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MEMORY CONTROLLER |
| TSPC106AVGSU/T83CE | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MEMORY CONTROLLER |
发布紧急采购，3分钟左右您将得到回复。