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参数资料
| 型号： | TSPC106AVGS66CG |
| 厂商： | E2V TECHNOLOGIES PLC |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, CBGA303 |
| 封装： | 21 X 25 MM, 3.84 MM HEIGHT, 1.27 MM PITCH, CICGA-303 |
| 文件页数： | 28/41页 |
| 文件大小： | 581K |
| 代理商： | TSPC106AVGS66CG |
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34
TSPC106A
2102C–HIREL–01/05
Notes:
1. PLL[0:3] settings not listed are reserved. Some PLL configurations may select bus, CPU or VCO frequencies which are not
useful, not supported or not tested. See “Input AC Specifications” on page 26 for valid SYSCLK and VCO frequencies.
2. 5:2 clock modes are only supported by TSPC106 Rev 4.0; earlier revisions do not support 5:2 clock modes. The 5:2 modes
require a 60x bus clock applied to the 60x clock phase (LBCLAIM) configuration input signal during power-on reset, hard
reset and coming out of sleep and suspend power saving modes.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal circuitry directly, the PLL is disabled and the
core/SYSCLK ratio is set for 1:1 mode operation. This mode is intended for factory use only.
Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.
4. In clock-off mode, no clocking occurs inside the TSPC106 regardless of the SYSCLK input.
5. PLL[0:3] = 0010 (1:1 Core/SYSCLK Ratio; X8 VCO Multiplier) exists on the chip but will fail to lock 50% of the time. There-
fore this configuration should not be used and 1:1 modes between 16 and 25 MHz are not supported.
PLL Power Supply
Filtering
The AV
DD power signal is provided on the 106 to provide power to the clock generation
phase-locked loop. To ensure stability of the internal clock, the power supplied to the
AV
DD input signal should be filtered using a circuit similar to the one shown in Figure 15.
The circuit should be placed as close as possible to the AV
DD pin to ensure it filters out
as much noise as possible.
Figure 15. PLL Power Supply Filter Circuit
Table 20. Core/VCO Frequencies and PLL Settings
PLL[0:3](1)
Core/SYSCL
Ratio
VCO Multiplier
Core Frequency (VCO Frequency) in MHz
PCI Bus
16.6 MHz
PCI Bus
20 MHz
PCI Bus
25 MHz
PCI Bus
33.3 MHz
0010
1:1
x8
33.3 (266)
0101
2:1
x4
40 (160)
50 (200)
66.6 (266)
0110
5:2(2)
x2
83.3 (166)
0111
5:2(2)
x4
41.6 (166)
50 (200)
62,5 (250)
83,3 (333)
1000
3:1
x2
75 (150)
1001
3:1
x4
60 (240)
75 (300)
0011
PLL Bypass(3)
PLL off
SYSCLK clocks core circuitry directly
1 x core/SYSCLK ratio implied
1111
Clock off(4)
PLL off
No core clocking occurs
GND
VDD
(3.3V)
10
10
F0.1 F
AVDD
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