参数资料
型号: TSPC106AVGS66CG
厂商: E2V TECHNOLOGIES PLC
元件分类: 总线控制器
英文描述: PCI BUS CONTROLLER, CBGA303
封装: 21 X 25 MM, 3.84 MM HEIGHT, 1.27 MM PITCH, CICGA-303
文件页数: 40/41页
文件大小: 581K
代理商: TSPC106AVGS66CG
8
TSPC106A
2102C–HIREL–01/05
Notes:
1. Some signals have dual functions and are shown more than once in this table.
2. All PCI signals are in little-endian bit order.
3. This test signal is for factory use only. It must be pulled up to VDD for normal device operation.
Signal Description
The signals on the TSPC106 are grouped as follows:
60x processor interface signals
L2 cache/multiple processor interface signals
Memory interface signals
PCI interface signals
Interrupt, clock and power management signals
IEEE 1149.1 interface signals
Configuration signals
Note:
A bar over a signal name indicates that the signal is active low, for example, address retry
(ARTRY) and transfer start (TS). Active-low signals are referred to as asserted (active)
when they are low and negated when they are high. Signals that are not active low such
as tag valid (TV) and nonmaskable interrupt (NMI) are referred to as asserted when they
are high and negated when they are low.
For multiple-function signals, outlined signal names refer to the alternate function(s) of
the signal being described. For example, the L2 controller signal, (tag output enable
TOE), has the alternate function data bus grant 1 (DBG1) when the TSPC106 is config-
ured for a second 60x processor.
TCK
F13
Clock
Input
TDI
B13
High
Input
TDO
E12
High
Output
TMS
D14
High
Input
TRST
H13
Low
Input
Power and Ground Signals
AV
DD
K9
High
Clock
LSSD_MODE(3)
G11
Low
Input
VDD
E10, E6, F11, F5, F7, G10, G12, G6, H5, H7, K10, K7, L12, M11, M5,
M7, N10, N12, N6, P11, P5, P7, R10, R6, J8, L8
High
Power
V
SS
E11, E7, F10, F12, F6, G5, G7, H12, H6, J7, L7, M10, M12, M6, N11, N5,
N7, P10, P12, P6, R11, R7, K8, J9, L9
Low
Ground
NC
H8, H9, M8, M9
––
Table 1. TSPC106 Pinout in 303-ball CBGA Package (Continued)
Signal Name
Pin Number
Active
I/O
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