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参数资料
| 型号： | TSPC106AVGS66CG |
| 厂商： | E2V TECHNOLOGIES PLC |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, CBGA303 |
| 封装： | 21 X 25 MM, 3.84 MM HEIGHT, 1.27 MM PITCH, CICGA-303 |
| 文件页数： | 15/41页 |
| 文件大小： | 581K |
| 代理商： | TSPC106AVGS66CG |
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TSPC106A
2102C–HIREL–01/05
Power Consumption
The TSPC106 provides hardware support for four levels of power reduction – the doze,
nap and sleep modes are invoked by register programming and the suspend mode is
invoked by assertion of an external signal. The design of the TSPC106 is fully static,
allowing internal logic states to be preserved during all power-saving modes. The follow-
ing sections describe the programmable power modes provided by the TSPC106.
Full-power Mode
This is the default power state of the TSPC106 following a hard reset with all internal
functional units fully powered and operating at full clock speed.
Doze Mode
In this power-saving mode, all the TSPC106 functional units are disabled except for PCI
address decoding, system RAM refreshing and 60x bus request monitoring (through
BRn). Once the doze mode is entered, a hard reset, a PCI transaction referenced to
system memory or a 60x bus request can bring the TSPC106 out of the doze mode and
into the full-on state. If the TSPC106 is awakened for a processor or PCI bus access,
the access is completed and the MC106 returns to the doze mode. The TSPC106’s
doze mode is totally independent of the power saving mode of the processor.
Nap Mode
Nap mode provides further power savings compared to doze mode. In nap mode, both
the processor and the TSPC106 are placed in a power reduction mode. In this mode,
only the PCI address decoding, system RAM refresh and the processor bus request
monitoring are still operating. Hard reset, a PCI bus transaction referenced to system
memory or a 60x bus request can bring the TSPC106 out of the nap mode. If the
TSPC106 is awakened by a PCI access, the access is completed and the TSPC106
returns to the nap mode. If the TSPC106 is awakened by a processor access, the
access is completed but the TSPC106 remains in the full-on state. When in the nap
mode, the PLL is required to be running and locked to the system clock (SYSCLK).
Sleep Mode
Sleep mode provides further power saving compared to the nap mode. As in nap mode,
both the processor and the TSPC106 are placed in a reduced power mode concurrently.
In sleep mode, no functional units are operating except the system RAM refresh logic,
which can continue (optionally) to perform the refresh cycles. A hard reset or a bus
request wakes the TSPC106 from sleep mode. The PLL and SYSCLK inputs may be
disabled by an external power management controller (PMC). For additional power sav-
ings, the PLL can be disabled by configuring the PLL[0:3] signals into the PLL-bypass
mode. The external PMC must enable the PLL, turn on SYSCLK and allow the PLL time
to lock before waking the system from sleep mode.
Suspend Mode
Suspend mode is activated through assertion of the SUSPEND signal. In suspend
mode, the TSPC106 may have its clock input and PLL shut down for additional power
savings. Memory refresh can be accomplished in two ways, either by using self-refresh
mode DRAMs or by using the RTC input on the TSPC106. To exit the suspend mode,
the system clock must be turned on in sufficient time to restart the PLL. After this time,
SUSPEND may be negated. In suspend mode, all outputs (except memory refresh) are
released to a high-impedance state and all inputs, including hard reset (HRST), are
ignored.
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