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| 型号： | UPD70F3261YGF-JBT-A |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | 14 X 20 MM, PLASTIC, QFP-100 |
| 文件页数： | 124/129页 |
| 文件大小： | 8549K |
| 代理商： | UPD70F3261YGF-JBT-A |
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CHAPTER 3 CPU FUNCTION
User’s Manual U16541EJ5V1UD
94
(2) Accessing specific on-chip peripheral I/O registers
This product has two types of internal system buses.
One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware.
The clock of the CPU bus and the clock of the peripheral bus are asynchronous. If an access to the CPU and
an access to the peripheral hardware conflict, therefore, unexpected illegal data may be transferred. If there is
a possibility of a conflict, the number of cycles for accessing the CPU changes when the peripheral hardware is
accessed, so that correct data is transferred. As a result, the CPU does not start processing of the next
instruction but enters the wait status. If this wait status occurs, the number of clocks required to execute an
instruction increases by the number of wait clocks shown below.
This must be taken into consideration if real-time processing is required.
When specific on-chip peripheral I/O registers are accessed, more wait states may be required in addition to
the wait states set by the VSWC register.
The access conditions and how to calculate the number of wait states to be inserted (number of CPU clocks)
at this time are shown below.
(1/2)
Peripheral Function
Register Name
Access
k
TPnCNT
Read
1 or 2
Write
1st access: No wait
Continuous write: 3 or 4
16-bit timer/event counter P (TMP)
(n = 0 to 5)
TPnCCR0, TPnCCR1
Read
1 or 2
TQ0CNT
Read
1 or 2
Write
1st access: No wait
Continuous write: 3 or 4
16-bit timer/event counter Q (TMQ)
TQ0CCR0 to TQ0CCR3
Read
1 or 2
Watchdog timer 2 (WDT2)
WDTM2
Write
(when WDT2 operating)
3
RTBL0
Write
(RTPC0.RTPOE0 bit = 0)
1
Real-time output function (RTO)
RTBH0
Write
(RTPC0.RTPOE0 bit = 0)
1
ADA0M0
Read
1 or 2
ADA0CR0 to ADA0CR11
Read
1 or 2
A/D converter
ADA0CR0H to ADA0CR11H
Read
1 or 2
I
2C00 to I2C02Note 1
IICS0 to IICS2
Read
1
<R>
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