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| 型号： | UPD70F3261YGF-JBT-A |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | 14 X 20 MM, PLASTIC, QFP-100 |
| 文件页数： | 2/129页 |
| 文件大小： | 8549K |
| 代理商： | UPD70F3261YGF-JBT-A |
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User’s Manual U16541EJ5V1UD
10
4.3.6
Port 7 .......................................................................................................................................122
4.3.7
Port 9 .......................................................................................................................................124
4.3.8
Port CM ...................................................................................................................................132
4.3.9
Port CT ....................................................................................................................................134
4.3.10
Port DH ....................................................................................................................................136
4.3.11
Port DL ....................................................................................................................................138
4.4
Block Diagrams..................................................................................................................... 141
4.5
Port Register Settings When Alternate Function Is Used ................................................ 171
4.6
Cautions ................................................................................................................................ 179
4.6.1
Cautions on setting port pins ...................................................................................................179
4.6.2
Cautions on bit manipulation instruction for port n register (Pn)...............................................182
4.6.3
Cautions on on-chip debug pins...............................................................................................183
4.6.4
Cautions on P05/INTP2/DRST pin...........................................................................................183
4.6.5
Cautions on P10, P11, and P53 pins when power is turned on ............................................... 183
4.6.6
Hysteresis characteristics ........................................................................................................183
4.6.7
Cautions on separate bus mode ..............................................................................................183
CHAPTER 5 BUS CONTROL FUNCTION .......................................................................................... 184
5.1
Features................................................................................................................................. 184
5.2
Bus Control Pins................................................................................................................... 185
5.2.1
Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed...............185
5.2.2
Pin status in each operation mode...........................................................................................185
5.3
Memory Block Function....................................................................................................... 186
5.4
External Bus Interface Mode Control Function ................................................................. 187
5.5
Bus Access ........................................................................................................................... 188
5.5.1
Number of clocks for access....................................................................................................188
5.5.2
Bus size setting function ..........................................................................................................189
5.5.3
Access by bus size ..................................................................................................................190
5.6
Wait Function ........................................................................................................................ 197
5.6.1
Programmable wait function ....................................................................................................197
5.6.2
External wait function...............................................................................................................198
5.6.3
Relationship between programmable wait and external wait ................................................... 199
5.6.4
Programmable address wait function.......................................................................................200
5.7
Idle State Insertion Function ............................................................................................... 201
5.8
Bus Hold Function................................................................................................................ 202
5.8.1
Functional outline.....................................................................................................................202
5.8.2
Bus hold procedure..................................................................................................................203
5.8.3
Operation in power save mode ................................................................................................203
5.9
Bus Priority ........................................................................................................................... 204
5.10
Bus Timing ............................................................................................................................ 205
CHAPTER 6 CLOCK GENERATION FUNCTION .............................................................................. 211
6.1
Overview................................................................................................................................ 211
6.2
Configuration ........................................................................................................................ 212
6.3
Registers ............................................................................................................................... 214
6.4
Operation............................................................................................................................... 219
6.4.1
Operation of each clock ...........................................................................................................219
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