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| 型号： | UPD70F3261YGF-JBT-A |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | 14 X 20 MM, PLASTIC, QFP-100 |
| 文件页数： | 61/129页 |
| 文件大小： | 8549K |
| 代理商： | UPD70F3261YGF-JBT-A |
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CHAPTER 1 INTRODUCTION
User’s Manual U16541EJ5V1UD
37
(10) Watchdog timer 2
A watchdog timer is provided on chip to detect inadvertent program loops, system abnormalities, etc.
Either the internal oscillation clock, the main clock, or the subclock can be selected as the source clock.
Watchdog timer 2 generates a non-maskable interrupt request signal (INTWDT2) or a system reset signal
(WDT2RES) after an overflow occurs.
(11) Serial interface
The V850ES/SG2 and V850ES/SG2-H include three kinds of serial interfaces: asynchronous serial interface
A (UARTA), 3-wire variable-length serial interface B (CSIB), and an I
2C bus interface (I2C).
In the case of UARTA, data is transferred via the TXDA0 to TXDA2 pins and RXDA0 to RXDA2 pins.
In the case of CSIB, data is transferred via the SOB0 to SOB4 pins, SIB0 to SIB4 pins, and SCKB0 to
SCKB4 pins.
In the case of I
2C, data is transferred via the SDA00 to SDA02 and SCL00 to SCL02 pins.
The I
2C is provided only in I2C bus versions (Y Products) (see Table 1-1).
(12) IEBus controller
The IEBus controller is a small-scale digital data transmission system for transferring data between units.
The IEBus controller is provided only in IEBus controller versions (see Table 1-1).
(13) CAN controller
The CAN controller is a small-scale digital data transmission system for transferring data between units.
The CAN controller is provided only in CAN controller versions (see Table 1-1).
(14) A/D converter
This 10-bit A/D converter includes 12 analog input pins. Conversion is performed using the successive
approximation method.
(15) D/A converter
A two-channel, 8-bit-resolution D/A converter that uses the R-2R ladder method is provided on chip.
(16) DMA controller
A 4-channel DMA controller is provided on chip. This controller transfers data between the internal RAM and
on-chip peripheral I/O devices in response to interrupt requests sent by on-chip peripheral I/O.
(17) ROM correction
A ROM correction function that replaces part of a program in the mask ROM with a program in the internal
RAM is provided. Up to four correction addresses can be specified.
(18) Key interrupt function
A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the key input pins (8
channels).
(19) Real-time output function
The real-time output function transfers preset 6-bit data to output latches upon the occurrence of a timer
compare register match signal.
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