参数资料
型号: XCV405E-6FG676I
厂商: Xilinx Inc
文件页数: 33/118页
文件大小: 0K
描述: IC FPGA 1.8V 676-BGA
产品变化通告: FPGA Family Discontinuation 18/Apr/2011
标准包装: 1
系列: Virtex®-E EM
LAB/CLB数: 2400
逻辑元件/单元数: 10800
RAM 位总计: 573440
输入/输出数: 404
门数: 129600
电源电压: 1.71 V ~ 1.89 V
安装类型: 表面贴装
工作温度: -40°C ~ 100°C
封装/外壳: 676-BGA
供应商设备封装: 676-FBGA(27x27)
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-2 (v3.0) March 21, 2014
Module 2 of 4
17
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Boundary-Scan Mode
In the boundary-scan mode, configuration is done through
the IEEE 1149.1 Test Access Port. Note that the
PROGRAM pin must be pulled High prior to reconfiguration.
A Low on the PROGRAM pin resets the TAP controller and
no JTAG operations can be performed.
Figure 18: SelectMAP Flowchart for Write Operations
Apply Power
Release INIT
If used to delay
configuration
On first FPGA
PROGRAM
from Low
to High
Set WRITE = Low
Enter Data Source
Set CS = Low
On first FPGA
Set CS = High
Apply Configuration Byte
INIT?
High
Low
Yes
No
Busy?
Low
High
Disable Data Source
Set WRITE = High
When all DONE pins
are released, DONE goes High
and start-up sequences complete.
If no errors,
later FPGAs enter start-up phase
releasing DONE.
If no errors,
first FPGAs enter start-up phase
releasing DONE.
Once per bitstream,
FPGA checks data using CRC
and pulls INIT Low on error.
FPGA makes a final
clearing pass and releases
INIT when finished.
FPGA starts to clear
configuration memory.
For any other FPGAs
ds003_17_090602
Repeat Sequence A
Configuration Completed
Sequence A
End of Data?
Yes
No
Figure 19: SelectMAP Write Abort Waveforms
CCLK
CS
WRITE
Abort
DATA[0:7]
BUSY
DS022_46_071702
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