参数资料
| 型号： | XCV405E-6FG676I |
| 厂商： | Xilinx Inc |
| 文件页数： | 51/118页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 1.8V 676-BGA |
| 产品变化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 标准包装： | 1 |
| 系列： | Virtex®-E EM |
| LAB/CLB数： | 2400 |
| 逻辑元件/单元数： | 10800 |
| RAM 位总计： | 573440 |
| 输入/输出数： | 404 |
| 门数： | 129600 |
| 电源电压： | 1.71 V ~ 1.89 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 676-BGA |
| 供应商设备封装： | 676-FBGA（27x27） |
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Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 2 of 4
DS025-2 (v3.0) March 21, 2014
34
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
The voltage reference signal is “banked” within the Virtex-E
device on a half-edge basis such that for all packages there
for a representation of the Virtex-E I/O banks. Within each
bank approximately one of every six I/O pins is automati-
cally configured as a VREF input. After placing a differential
amplifier input signal within a given VREF bank, the same
external source must drive all I/O pins configured as a VREF
input.
IBUF placement restrictions require that any differential
amplifier input signals within a bank be of the same stan-
dard. How to specify a specific location for the IBUF via the
LOC property is described below. Table 19 summarizes the
Virtex-E input standards compatibility requirements.
An optional delay element is associated with each IBUF.
When the IBUF drives a flip-flop within the IOB, the delay
element by default activates to ensure a zero hold-time
requirement. The NODELAY=TRUE property overrides this
default.
When the IBUF does not drive a flip-flop within the IOB, the
delay element de-activates by default to provide higher per-
formance. To delay the input signal, activate the delay ele-
ment with the DELAY=TRUE property.
IBUFG
Signals used as high fanout clock inputs to the Virtex-E
device should drive a global clock input buffer (IBUFG) via
an external input port in order to take advantage of one of
the four dedicated global clock distribution networks. The
output of the IBUFG should only drive a CLKDLL, CLK-
DLLHF, or a BUFG symbol. The generic Virtex-E IBUFG
symbol appears in Figure 39.
The extension to the base name determines which I/O stan-
dard is used by the IBUFG. With no extension specified for
the generic IBUFG symbol, the assumed standard is
LVTTL.
The following list details variations of the IBUFG symbol.
IBUFG
IBUFG_LVCMOS2
IBUFG_PCI33_3
IBUFG_PCI66_3
IBUFG_GTL
IBUFG_GTLP
IBUFG_HSTL_I
IBUFG_HSTL_III
IBUFG_HSTL_IV
IBUFG_SSTL3_I
IBUFG_SSTL3_II
IBUFG_SSTL2_I
IBUFG_SSTL2_II
IBUFG_CTT
IBUFG_AGP
IBUFG_LVCMOS18
IBUFG_LVDS
IBUFG_LVPECL
When the IBUFG symbol supports an I/O standard that
requires a differential amplifier input, the IBUFG automati-
cally configures as a differential amplifier input buffer. The
low-voltage I/O standards with a differential amplifier input
require an external reference voltage input VREF.
The voltage reference signal is “banked” within the Virtex-E
device on a half-edge basis such that for all packages there
for a representation of the Virtex-E I/O banks. Within each
bank approximately one of every six I/O pins is automati-
cally configured as a VREF input. After placing a differential
amplifier input signal within a given VREF bank, the same
external source must drive all I/O pins configured as a VREF
input.
IBUFG placement restrictions require any differential ampli-
fier input signals within a bank be of the same standard. The
LOC property can specify a location for the IBUFG.
Figure 38: Virtex-E I/O Banks
Table 19:
Xilinx Input Standards Compatibility
Requirements
Rule 1
Standards with the same input VCCO, output VCCO,
and VREF can be placed within the same bank.
ds022_42_012100
Bank 0
GCLK3
GCLK2
GCLK1
GCLK0
Bank 1
Bank 5
Bank 4
Virtex-E
Device
Bank
7
Bank
6
Bank
2
Bank
3
Figure 39: Virtex-E Global Clock Input Buffer (IBUFG)
Symbol
O
I
IBUFG
x133_03_111699
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相关代理商/技术参数 |
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|---|---|
| XCV405E-6FG900C | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-6FG900I | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-7BG404C | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-7BG404I | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-7BG556C | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
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