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| 型号： | A42MX24-3VQ100B |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件页数： | 16/93页 |
| 文件大小： | 854K |
| 代理商： | A42MX24-3VQ100B |
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23
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
8
TABLE 37. BC CONDITION CODES
BIT
CODE
LT/GP0
EQ/GP1
RETRY0
RETRY1
RETRY0
RETRY1
D
E
GP2
GP3
GP4
GP5
GP6
GP7
NORESP
GD BLK
XFER
NAME
(BIT 4 = 0)
These two bits reflect the retry status of the most recent message. The number of times that the mes-
sage was retried is delineated by these two bits as shown below:
RETRY COUNT 1
RETRY COUNT 0
Number of
(bit 14)
(bit 13)
Message Retries
0
1
0
N/A
1
2
FUNCTIONAL DESCRIPTION
INVERSE
(BIT 4 = 1)
GT-EQ/
GP0
NE/GP1
0
ALWAYS
Less than or GP0 flag. This bit is set or cleared based on the results of the compare. If the value of the
CMT's parameter is less than the value of the message time counter, then the LT/GP0 and NE/GP1
flags will be set, while the GT-EQ/GP0 and EQ/GP1 flags will be cleared. If the value of the CMT's
parameter is equal to the value of the message time counter, then the GT-EQ/GP0 and EQ/GP1 flags
will be set, while the LT/GP0 and NE/GP1 flags will be cleared. If the value of the CMT's parameter is
greater than the current value of the message time counter, then the GT-EQ/GP0 and NE/GP1 flags will
be set, while the LT/GP0 and EQ/GP1 flags will be cleared. Also, General Purpose Flag 1 may be also
be set or cleared by a FLG operation.
NEVER
F
GP2
GP3
GP4
GP5
GP6
GP7
1
RESP
Equal Flag. This bit is set or cleared after CFT or CMT operation. If the value of the CMT's parameter is
equal to the value of the message time counter, then the EQ/GP1 flag will be set and the NE/GP1 bit
will be cleared. If the value of the CMT's parameter is not equal to the value of the message time
counter, then the NE/GP1 flag will be set and the EQ/GP1bit will be cleared. Also, General Purpose
Flag 1 may be also be set or cleared by a FLG operation.
GD BLK
XFER
BAD
MESSAGE
GOOD
MESSAGE
The ALWAYS flag should be set (bit 4 = 0) to designate an instruction as unconditional. The NEVER bit
(bit 4 = 1) can be used to implement a NOP or "skip" instruction.
C
BAD MESSAGE indicates either a format error, loop test fail, or no response error for the most recent
message. Note that a "Status Set" condition has no effect on the "BAD MESSAGE/GOOD MESSAGE"
condition code.
FMT ERR
9
FMT ERR indicates that the received portion of the most recent message contained one or more viola-
tions of the 1553 message validation criteria (sync, encoding, parity, bit count, word count, etc.), or the
RT's status word received from a responding RT contained an incorrect RT address field.
MASKED
STATUS
BIT
MASKED
STATUS
BIT
B
General Purpose Flags may be set, cleared, or toggled by a FLG operation. The host processor can
set, clear, or toggle these flags in the same way as the FLG instruction by means of the BC GENERAL
PURPOSE FLAG REGISTER.
Indicates that one or both of the following conditions have occurred for the most recent message: (1) If
one (or more) of the Status Mask bits (14 through 9) in the BC Control Word is logic "0" and the corre-
sponding bit(s) is (are) set (logic "1") in the received RT Status Word. In the case of the RESERVED
BITS MASK (bit 9) set to logic "0," any or all of the 3 Reserved Status Word bits being set will result in
a MASKED STATUS SET condition; and/or (2) If BROADCAST MASK ENABLED/XOR (bit 11 of
Configuration Register #4) is logic "1" and the MASK BROADCAST bit of the message's BC Control
Word is logic "0" and the BROADCAST COMMAND RECEIVED bit in the received RT Status Word is
logic "1."
2
3
4
5
6
7
NORESP indicates that an RT has either not responded or has responded later than the BC No
Response Timeout time. The Mini-ACE
Mark3's No Response Timeout Time is defined per
MIL-STD-1553B as the time from the mid-bit crossing of the parity bit of the last word transmitted by
the BC to the mid-sync crossing of the RT Status Word. The value of the No Response Timeout value
is programmable from among the nominal values 18.5, 22.5, 50.5, and 130 s (±1 s) by means of bits
10 and 9 of Configuration Register #5.
A
For the most recent message, GD BLK XFER will be set to logic "1" following completion of a valid
(error-free) RT-to-BC transfer, RT-to-RT transfer, or transmit mode code with data message. This bit is
set to logic "0" following an invalid message. GOOD DATA BLOCK TRANSFER is always logic "0" fol-
lowing a BC-to-RT transfer, a mode code with data, or a mode code without data. The Loop Test has
no effect on GOOD DATA BLOCK TRANSFER. GOOD DATA BLOCK TRANSFER may be used to
determine if the transmitting portion of an RT-to-RT transfer was error free.
相关PDF资料 |
PDF描述 |
|---|---|
| A42MX36-2PQ100B | 40MX and 42MX FPGA Families |
| A42MX36-2PQ100ES | 40MX and 42MX FPGA Families |
| A42MX36-2TQ100 | 40MX and 42MX FPGA Families |
| A42MX36-2TQ100A | 40MX and 42MX FPGA Families |
| A42MX36-2TQ100B | 40MX and 42MX FPGA Families |
相关代理商/技术参数 |
参数描述 |
|---|---|
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