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| 型号： | A42MX24-3VQ100B |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件页数： | 35/93页 |
| 文件大小： | 854K |
| 代理商： | A42MX24-3VQ100B |
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40
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
CLOCK IN
VALID
t7
t3
t8
t11
t13
t15
VALID
t10
t4
t9
t12
t19
;
;;
VALID
t16
t17
SELECT
(Note 2,7)
(Note 2)
(Note 3,4,7)
(Note 4,5)
STRBD
MEM/REG
RD/WR
IOEN
(Note 2,6)
(Note 6)
(Note 7,8,9)
READYD
A15-A0
D15-D0
;
;;
;;;
;;
t5
t1
t2
t6
t14
t18
FIGURE 13. CPU READING RAM / REGISTER (16-BIT BUFFERED, NONZERO WAIT)
NOTES:
1.
For the 16-bit buffered nonzero wait configuration, TRANSPARENT/BUFFERED must be connected to logic "0". ZERO_WAIT and DTREQ / 16/8
must be connected to logic "1". The inputs TRIGGER_SEL and MSB/LSB may be connected to either Vcc or ground.
2.
SELECT and STRBD may be tied together. IOEN goes low on the first rising CLK edge when SELECT STRBD is sampled low (satisfying t1)
and the Mark3’s protocol/memory management logic is not accessing the internal RAM. When this occurs, IOEN goes low, starting the transfer
cycle. After IOEN goes low, SELECT may be released high.
3.
MEM/REG must be presented high for memory access, low for register access.
4.
MEM/REG and RD/WR are buffered transparently until the first falling edge of CLK after IOEN goes low. After this CLK edge, MEM/REG and
RD/WR become latched internally.
5.
The logic sense for RD/WR in the diagram assumes that POLARITY_SEL is connected to logic "1". If POLARITY_SEL is connected to logic "0",
RD/WR must be asserted low to read.
6.
The timing for IOEN, READYD and D15-D0 assumes a 50 pf load. For loading above 50 pf, the validity of IOEN, READYD, and D15-D0 is delayed
by an additional 0.14 ns/pf typ, 0.28 ns/pf max.
7.
The timing for A15-A0, MEM/REG and SELECT assumes that ADDR-LAT is connected to logic "1". Refer to Address Latch timing for additional
details.
8.
The address bus A15-A0 is internally buffered transparently until the first rising edge of CLK after IOEN goes low. After this CLK edge, A15-A0
become latched internally.
9.
Setup time given for use in worst case timing calculations. None of the Mark3’s input signals are required to be synchronized to the system clock.
When SELECT and STRBD do not meet the setup time of t1, but occur during the setup window of an internal flip-flop, an additional clock cycle
will be inserted between the falling clock edge that latches MEM/REG and RD/WR and the rising clock edge that latches the Address (A15-A0).
When this occurs, the delay from IOEN falling to READYD falling (t11) increases by one clock cycle and the address hold time (t10) must be
increased by one clock cycle.
相关PDF资料 |
PDF描述 |
|---|---|
| A42MX36-2PQ100B | 40MX and 42MX FPGA Families |
| A42MX36-2PQ100ES | 40MX and 42MX FPGA Families |
| A42MX36-2TQ100 | 40MX and 42MX FPGA Families |
| A42MX36-2TQ100A | 40MX and 42MX FPGA Families |
| A42MX36-2TQ100B | 40MX and 42MX FPGA Families |
相关代理商/技术参数 |
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