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| 型号： | A42MX24-3VQ100B |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件页数： | 48/93页 |
| 文件大小： | 854K |
| 代理商： | A42MX24-3VQ100B |
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52
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
SELECT (I)
66
Device Select.
Generally connected to a CPU address decoder output to select the Mark3 for a transfer to/from either
RAM or register.
STRBD (I)
68
Strobe Data.
Used in conjunction with SELECT to initiate and control the data transfer cycle between the host processor
and the Mark3. STRBD must be asserted low through the full duration of the transfer cycle.
RD / WR (I)
71
Read/Write.
For host processor access, RD/WR selects between reading and writing. In the 16-bit buffered mode, if
POL_SEL is logic "0”, then RD/WR should be low (logic "0") for read accesses and high (logic "1") for write
accesses. If POL_SEL is logic "1", or the interface is configured for a mode other than 16-bit buffered
mode, then RD/WR is high (logic "1") for read accesses and low (logic "0") for write accesses.
ADDR_LAT(I) /
MEMOE (O)
20
Memory Output Enable or Address Latch.
In buffered mode, the ADDR_LAT input is used to configure the buffers for A15-A0, SELECT, MEM/REG,
and MSB/LSB (for 8-bit mode only) in latched mode (when low) or transparent mode (when high). That is,
the Mark3's internal transparent latches will track the values on A15-A0, SELECT, MEM/REG, and
MSB/LSB when ADDR_LAT is high, and latch the values when ADDR_LAT goes low.
In general, for interfacing to processors with a non-multiplexed address/data bus, ADDR_LAT should be
hardwired to logic "1". For interfacing to processors with a multiplexed address/data bus, ADDR_LAT
should be connected to a signal that indicates a valid address when ADDR_LAT is logic "1".
In transparent mode, MEMOE output signal is used to enable data outputs for external RAM read cycles
(normally connected to the OE input signal on external RAM chips).
ZEROWAIT (I) /
MEMWR (O)
28
Memory Write or Zero Wait.
In buffered mode, input signal (ZEROWAIT) used to select between the zero wait mode (ZEROWAIT = "0")
and the non-zero wait mode (ZEROWAIT = "1").
In transparent mode, active low output signal (MEMWR) asserted low during memory write transfers to
strobe data into external RAM (normally connected to the WR input signal on external RAM chips).
16 / 8 (I) /
DTREQ (O)
29
Data Transfer Request or Data Bus Select.
In buffered mode, input signal 16/8 used to select between the 16 bit data transfer mode (16/8= "1") and
the 8-bit data transfer mode (16/8 = "0").
In transparent mode (16-bit only), active low level output signal DTREQ used to request access to the
processor/RAM interface bus (address and data buses).
MSB / LSB (I) /
DTGRT (I)
72
Data Transfer Grant or Most Significant Byte/Least Significant Byte.
In 8-bit buffered mode, input signal (MSB/LSB) used to indicate which byte is currently being transferred
(MSB or LSB). The logic sense of MSB/LSB is controlled by the POL_SEL input. MSB/LSB is not used in
the 16-bit buffered mode.
In transparent mode, active low input signal (DTGRT) asserted in response to the DTREQ output to indi-
cate that control of the external processor/RAM bus has been transferred from the host processor to the
Mark3.
TABLE 53. PROCESSOR INTERFACE CONTROL
SIGNAL NAME
DESCRIPTION
BU-6474XF/GX
BU-6484XF/GX
BU-64863F/GX
PIN
FLAT PACK AND GULL WING PACKAGES - SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS (CONT.)
相关PDF资料 |
PDF描述 |
|---|---|
| A42MX36-2PQ100B | 40MX and 42MX FPGA Families |
| A42MX36-2PQ100ES | 40MX and 42MX FPGA Families |
| A42MX36-2TQ100 | 40MX and 42MX FPGA Families |
| A42MX36-2TQ100A | 40MX and 42MX FPGA Families |
| A42MX36-2TQ100B | 40MX and 42MX FPGA Families |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A42MX24-FPL84 | 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A42MX24-FPLG84 | 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A42MX24-FPQ160 | 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A42MX24-FPQ208 | 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A42MX24-FPQG160 | 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
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