- 您现在的位置：买卖IC网 > PDF目录298744 > A42MX24-3VQ100B (Electronic Theatre Controls, Inc.) 40MX and 42MX FPGA Families PDF资料下载
参数资料
| 型号： | A42MX24-3VQ100B |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件页数： | 27/93页 |
| 文件大小： | 854K |
| 代理商： | A42MX24-3VQ100B |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页当前第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页
33
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
RT COMMAND ILLEGALIZATION
The Mini-ACE Mark3 provides an internal mechanism for RT
Command Word illegalizing. By means of a 256-word area in
shared RAM, the host processor may designate that any mes-
sage be illegalized, based on the command word T/R bit, sub-
address, and word count/mode code fields. The Mini-ACE Mark3
illegalization scheme provides the maximum in flexibility, allow-
ing any subset of the 4096 possible combinations of broad-
cast/own address, T/R bit, subaddress, and word count/mode
code to be illegalized.
The address map of the Mini-ACE Mark3's illegalizing table is
illustrated in TABLE 41.
BUSY BIT
The Mini-ACE Mark3 RT provides two different methods for set-
ting the Busy status word bit: (1) globally, by means of
Configuration Register #1; or (2) on a T/R-bit/subaddress basis,
by means of a RAM lookup table. If the host CPU asserts the
BUSY bit to logic “0” in Configuration Register #1, the Mini-ACE
Mark3 RT will respond to all non-broadcast commands with the
Busy bit set in its RT Status Word.
Alternatively, there is a Busy lookup table in the Mini-ACE Mark3
shared RAM. By means of this table, it is possible for the host
processor to set the busy bit for any selectable subset of the 128
combinations of broadcast/own address, T/R bit, and subaddress.
If the busy bit is set for a transmit command, the Mini-ACE Mark3
RT will respond with the busy bit set in the status word, but will
not transmit any data words. If the busy bit is set for a receive
command, the RT will also respond with the busy status bit set.
There are two programmable options regarding the reception of
data words for a non-mode code receive command for which the
RT is busy: (1) to transfer the received data words to shared
RAM; or (2) to not transfer the data words to shared RAM.
RT ADDRESS
The Mini-ACE Mark3 offers several different options for desig-
nating the Remote Terminal address. These include the follow-
ing: (1) hardwired, by means of the 5 RT ADDRESS inputs, and
the RT ADDRESS PARITY input; (2) by means of the RT
ADDRESS (and PARITY) inputs, but latched via hardware, on
the rising edge of the RT_AD_LAT input signal; (3) input by
means of the RT ADDRESS (and PARITY) inputs, but latched via
host software; and (4) software programmable, by means of an
internal register. In all four configurations, the RT address is
readable by the host processor.
RT BUILT-IN-TEST (BIT) WORD
The bit map for the Mini-ACE Mark3's internal RT Built-in-Test
(BIT) Word is indicated in TABLE 42.
RT AUTO-BOOT OPTION
If utilized, the RT pin-programmable auto-boot option allows the
Mini-ACE Mark3 RT to automatically initialize as an active
COMMAND WORD CONTENTS ERROR
0 (LSB)
RT-to-RT 2ND COMMAND WORD ERROR
1
RT-to-RT NO RESPONSE ERROR
2
TRANSMITTER SHUTDOWN B
RT-to-RT GAP / SYNC ADDRESS ERROR
3
PARITY / MANCHESTER ERROR RECEIVED
4
INCORRECT SYNC RECEIVED
5
LOW WORD COUNT
6
HIGH WORD COUNT
7
BIT TEST FAILURE
8
TERMINAL FLAG INHIBITED
9
TRANSMITTER SHUTDOWN A
10
HANDSHAKE FAILURE
12
LOOP TEST FAILURE A
13
LOOP TEST FAILURE B
14
TRANSMITTER TIMEOUT
15(MSB)
DESCRIPTION
BIT
11
TABLE 42. RT BIT WORD
remote terminal with the Busy status word bit set to logic "1"
immediately following power turn-on. This is a useful feature for
MIL-STD-1760 applications, in which the RT is required to be
responding within 150 ms after power-up. This feature is avail-
able for versions of the Mini-ACE Mark3 with 4K words of RAM.
OTHER RT FEATURES
The Mini-ACE Mark3 includes options for the Terminal flag sta-
tus word bit to be set either under software control and/or auto-
matically following a failure of the loopback self-test. Other soft-
ware programmable RT options include software programmable
RT status and RT BIT words, automatic clearing of the Service
Request bit following receipt of a Transmit vector word mode
command, options regarding Data Word transfers for the Busy
and Message error (illegal) Status word bits, and options for the
handling of 1553A and reserved mode codes.
MONITOR ARCHITECTURE
The Mini-ACE Mark3 includes three monitor modes:
(1) A Word Monitor mode
(2) A selective message monitor mode
(3) A combined RT/message monitor mode
For new applications, it is recommended that the selective mes-
sage monitor mode be used, rather than the word monitor mode.
Besides providing monitor filtering based on RT address, T/R bit,
and subaddress, the message monitor eliminates the need to
determine the start and end of messages by software.
相关PDF资料 |
PDF描述 |
|---|---|
| A42MX36-2PQ100B | 40MX and 42MX FPGA Families |
| A42MX36-2PQ100ES | 40MX and 42MX FPGA Families |
| A42MX36-2TQ100 | 40MX and 42MX FPGA Families |
| A42MX36-2TQ100A | 40MX and 42MX FPGA Families |
| A42MX36-2TQ100B | 40MX and 42MX FPGA Families |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A42MX24-FPL84 | 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A42MX24-FPLG84 | 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A42MX24-FPQ160 | 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A42MX24-FPQ208 | 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A42MX24-FPQG160 | 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
发布紧急采购，3分钟左右您将得到回复。