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参数资料
| 型号： | A42MX24-3VQ100B |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件页数： | 63/93页 |
| 文件大小： | 854K |
| 代理商： | A42MX24-3VQ100B |
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66
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
UPADDREN (I)
Logic "1"
C12
This signal is used to control the function of the upper 4 address
inputs (A15-A12). If UPADDREN is connected to logic "1", then these
four signals operate as address lines A15-A12. If UPADDREN is con-
nected to logic "0", then A15 and A14 function as CLK_SEL_1 and
CLK_SEL_0 respectively; A13 MUST be connected to LOGIC "1"; and
A12 functions as RTBOOT.
TABLE 64. MISCELLANEOUS
SIGNAL NAME
DESCRIPTION
BU-64840B3
BU-64860B3
BALL
F7
SLEEPIN (I)
-
This signal is used to control the transceiver sleep (power-down) cir-
cuitry. If SLEEPIN is connected to logic "0", the transceivers are fully
powered and operate normally. If SLEEPIN is connected to logic "1",
the transceivers are in sleep mode (dormant, low-power mode) of
operation and are NOT operational.
R4
INCMD (O)
H16
For BC, RT, or Selective Message Monitor modes, INCMD is asserted
low whenever a message is being processed by the Micro-ACE-TE. In
Word Monitor mode, INCMD will be asserted low for as long as the
monitor is online.
P17
MCRST (O)
B13
For RT mode MCRST will be asserted low for two clock cycles follow-
ing receipt of a Reset remote terminal mode command.
D11
RSTBITEN (I)
M18
If this input is set to logic "1", the Built-In-Self-Test (BIST) will be
enabled after hardware reset (for example, following power-up). A logic
"0" input disables both the power-up and user-initiated automatic BIST.
L14
INT (O)
D17
Interrupt Request output. If the LEVEL/PULSE interrupt bit (bit 3) of
Configuration Register #2 is logic "0", a negative pulse of approxi-
mately 500 ns in width is output on INT to signal an interrupt request.
If LEVEL/PULSE is high, a low level interrupt request output will be
asserted on INT. The level interrupt will be cleared (high) after either:
(1) The processor writes a value of logic "1" to INTERRUPT RESET,
bit 2 of the Start/Reset Register; or (2) If bit 4 of Configuration
Register #2, INTERRUPT STATUS AUTO-CLEAR is logic "1" then it
will only be necessary to read the Interrupt Status Register (#1 and/or
#2) that is requesting an interrupt enabled by the corresponding
Interrupt Mask Register. However, for the case where both Interrupt
Status Register #1 and Interrupt Status Register #2 have bits set
reflecting interrupt events, it will be necessary to read both interrupt
status registers in order to clear INT.
D18
CLOCK_IN (I)
M9
20 MHz, 16 MHz, 12 MHz, or 10 MHz clock input.
T10
MSTCLR (I)
B11
Master Clear. Negative true Reset input, normally asserted low follow-
ing power turn-on.
R18
TAG_CLK (I)
D18
Time Tag Clock. External clock that may be used to increment the
Time Tag Register. This option is selected by setting Bits 7, 8 and 9 of
Configuration Register # 2 to Logic "1".
F14
TX_INH_A (I)
TX_INH_B (I)
A14
Transmitter inhibit inputs for Channel A and Channel B, MIL-STD-
1553 transmitters. For normal operation, these inputs should be con-
nected to logic "0". To force a shutdown of Channel A and/or Channel
B, a value of logic "1" should be applied to the respective TX_INH
input.
A14
C13
B14
BU-64743B8
BU-64843B8
BU-64863B8
BALL
4K RAM
(BU-64743B8
BU-6484XBX)
64K RAM
(BU-6486XBX)
BALL GRID ARRAY PACKAGE - SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS (CONT.)
相关PDF资料 |
PDF描述 |
|---|---|
| A42MX36-2PQ100B | 40MX and 42MX FPGA Families |
| A42MX36-2PQ100ES | 40MX and 42MX FPGA Families |
| A42MX36-2TQ100 | 40MX and 42MX FPGA Families |
| A42MX36-2TQ100A | 40MX and 42MX FPGA Families |
| A42MX36-2TQ100B | 40MX and 42MX FPGA Families |
相关代理商/技术参数 |
参数描述 |
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| A42MX24-FPL84 | 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A42MX24-FPLG84 | 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A42MX24-FPQ160 | 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A42MX24-FPQ208 | 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A42MX24-FPQG160 | 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
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