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| 型号： | A42MX24-3VQ100B |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件页数： | 59/93页 |
| 文件大小： | 854K |
| 代理商： | A42MX24-3VQ100B |
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62
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
SELECT (I)
B12
Device Select.
Generally connected to a CPU address decoder output to select the Mark3 for a
transfer to/from either RAM or register.
TABLE 62. PROCESSOR INTERFACE CONTROL
SIGNAL NAME
DESCRIPTION
BU-64840B3
BU-64860B3
BALL
B12
STRBD (I)
A12
Strobe Data.
Used in conjunction with SELECT to initiate and control the data transfer cycle
between the host processor and the Mark3. STRBD must be asserted low through
the full duration of the transfer cycle.
A12
ADDR_LAT(I) /
MEMOE (O)
L9
Memory Output Enable or Address Latch.
In buffered mode, the ADDR_LAT input is used to configure the buffers for A15-
A0, SELECT, MEM/REG, and MSB/LSB (for 8-bit mode only) in latched mode
(when low) or transparent mode (when high). That is, the Mark3's internal trans-
parent latches will track the values on A15-A0, SELECT, MEM/REG, and
MSB/LSB when ADDR_LAT is high, and latch the values when ADDR_LAT goes
low.
In general, for interfacing to processors with a non-multiplexed address/data bus,
ADDR_LAT should be hardwired to logic "1". For interfacing to processors with a
multiplexed address/data bus, ADDR_LAT should be connected to a signal that
indicates a valid address when ADDR_LAT is logic "1".
In transparent mode, MEMOE output signal is used to enable data outputs for
external RAM read cycles (normally connected to the OE input signal on external
RAM chips).
U10
ZEROWAIT (I) /
MEMWR (O)
M10
Memory Write or Zero Wait.
In buffered mode, input signal (ZEROWAIT) used to select between the zero wait
mode (ZEROWAIT = "0") and the non-zero wait mode (ZEROWAIT = "1").
In transparent mode, active low output signal (MEMWR) asserted low during
memory write transfers to strobe data into external RAM (normally connected to
the WR input signal on external RAM chips).
T8
16 / 8 (I) /
DTREQ (O)
L10
Data Transfer Request or Data Bus Select.
In buffered mode, input signal 16/8 used to select between the 16 bit data transfer
mode (16/8 = "1") and the 8-bit data transfer mode (16/8 = "0").
In transparent mode (16-bit only), active low level output signal DTREQ used to
request access to the processor/RAM interface bus (address and data buses).
R17
MSB / LSB (I) /
DTGRT (I)
J7
Data Transfer Grant or Most Significant Byte/Least Significant Byte.
In 8-bit buffered mode, input signal (MSB/LSB) used to indicate which byte is cur-
rently being transferred (MSB or LSB). The logic sense of MSB/LSB is controlled
by the POL_SEL input. MSB/LSB is not used in the 16-bit buffered mode.
In transparent mode, active low input signal (DTGRT) asserted in response to the
DTREQ output to indicate that control of the external processor/RAM bus has
been transferred from the host processor to the Mark3.
B6
RD / WR (I)
A11
Read/Write.
For host processor access, RD/WR selects between reading and writing. In the
16-bit buffered mode, if POL_SEL is logic "0”, then RD/WR should be low (logic
"0") for read accesses and high (logic "1") for write accesses. If POL_SEL is logic
"1", or the interface is configured for a mode other than 16-bit buffered mode, then
RD/WR is high (logic "1") for read accesses and low (logic "0") for write accesses.
B11
BU-64743B8
BU-64843B8
BU-64863B8
BALL
BALL GRID ARRAY PACKAGE - SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS (CONT.)
相关PDF资料 |
PDF描述 |
|---|---|
| A42MX36-2PQ100B | 40MX and 42MX FPGA Families |
| A42MX36-2PQ100ES | 40MX and 42MX FPGA Families |
| A42MX36-2TQ100 | 40MX and 42MX FPGA Families |
| A42MX36-2TQ100A | 40MX and 42MX FPGA Families |
| A42MX36-2TQ100B | 40MX and 42MX FPGA Families |
相关代理商/技术参数 |
参数描述 |
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