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| 型号： | A42MX24-3VQ100B |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件页数： | 31/93页 |
| 文件大小： | 854K |
| 代理商： | A42MX24-3VQ100B |
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Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
Register. For each message processed, the value of the Time
Tag Register is loaded into the second location of the respective
descriptor stack entry ("TIME TAG WORD") for both the BC and
RT modes.
The functionality involving the Time Tag Register that's compati-
ble with ACE/Mini-ACE (Plus) includes: the capability to issue an
interrupt request and set a bit in the Interrupt Status Register
when the Time Tag Register rolls over FFFF to 0000; for RT
mode, the capability to automatically clear the Time Tag Register
following reception of a Synchronize (without data) mode com-
mand, or to load the Time Tag Register following a Synchronize
(with data) mode command.
Additional time tag features supported by the Mini-ACE Mark3
include the capability for the BC to transmit the contents of the
Time Tag Register as the data word for a Synchronize (with data)
mode command; the capability for the RT to "filter" the data word
for the Synchronize with data mode command, by only loading
the Time Tag Register if the LSB of the received data word is "0";
an instruction enabling the BC Message Sequence Control
engine to load the Time Tag Register with a specified value; and
an instruction enabling the BC Message Sequence Control
engine to write the value of the Time Tag Register to the General
Purpose Queue.
INTERRUPTS
The Mini-ACE Mark3 series terminals provide many program-
mable options for interrupt generation and handling. The inter-
rupt output pin (INT) has three software programmable modes of
operation: a pulse, a level output cleared under software control,
or a level output automatically cleared following a read of the
Interrupt Status Register (#1 or #2).
Individual interrupts are enabled by the two Interrupt Mask
Registers. The host processor may determine the cause of the
interrupt by reading the two Interrupt Status Registers, which
provide the current state of interrupt events and conditions. The
Interrupt Status Registers may be updated in two ways. In one
interrupt handling mode, a particular bit in Interrupt Status
Register #1 or #2 will be updated only if the event occurs and the
corresponding bit in Interrupt Mask Register #1 or #2 is enabled.
In the enhanced interrupt handling mode, a particular bit in one
of the Interrupt Status Registers will be updated if the event/con-
dition occurs regardless of the value of the corresponding
Interrupt Mask Register bit. In either case, the respective
Interrupt Mask Register (#1 or #2) bit is used to enable an inter-
rupt for a particular event/condition.
The Mini-ACE Mark3 supports all the interrupt events from
ACE/Mini-ACE (Plus), including RAM Parity Error, Transmitter
Timeout, BC/RT Command Stack Rollover, MT Command Stack
and Data Stack Rollover, Handshake Error, BC Retry, RT Address
Parity Error, Time Tag Rollover, RT Circular Buffer Rollover, BC
Message, RT Subaddress, BC End-of-Frame, Format Error, BC
Status Set, RT Mode Code, MT Trigger, and End-of-Message.
For the Mini-ACE Mark3's Enhanced BC mode, there are four
user-defined interrupt bits. The BC Message Sequence Control
Engine includes an instruction enabling it to issue these inter-
rupts at any time.
For RT and Monitor modes, the Mini-ACE Mark3 architecture
includes an Interrupt Status Queue. This provides a mechanism
for logging messages that result in interrupt requests. Entries to
the Interrupt Status Queue may be filtered such that only valid
and/or invalid messages will result in entries on the queue.
The Mini-ACE Mark3 incorporates additional interrupt conditions
beyond the ACE/Mini-ACE (Plus), based on the addition of
Interrupt Mask Register #2 and Interrupt Status Register #2. This
is accomplished by chaining the two Interrupt Status Registers
using the INTERRUPT CHAIN BIT (bit 0) in Interrupt Status
Register #2 to indicate that an interrupt has occurred in Interrupt
Status Register #1. Additional interrupts include "Self-Test
Completed", masking bits for the Enhanced BC Control
Interrupts, 50% Rollover interrupts for RT Command Stack, RT
Circular Buffers, MT Command Stack, and MT Data Stack; BC
Op Code Parity Error, (RT) Illegal Command, (BC) General
Purpose Queue or (RT/MT) Interrupt Status Queue Rollover,
Call Stack Pointer Register Error, BC Trap Op Code, and the four
User-Defined interrupts for the Enhanced BC mode.
BUILT-IN TEST
A salient feature of the Mini-ACE Mark3 is its highly autonomous
self-test capability. This includes both protocol and RAM self-
tests. Either or both of these self-tests may be initiated by com-
mand(s) from the host processor.
The protocol test consists of a comprehensive toggle test of the
terminal's logic. The test includes testing of all registers,
Manchester decoders, protocol logic, and memory management
logs. This test is completed in approximately 32,000 clock cycles.
That is, about 1.6 ms with a 20 MHz clock, 2.0 ms at 16 MHz, 2.7
ms at 12 MHz, and 3.2 ms at 10 MHz.
There is also a separate built-in test (BIT) for the Mini-ACE
Mark3's 4K X 16 or 64K X 16 shared RAM. This test consists of
writing and then reading/verifying the two walking patterns "data
= address" and "data = address inverted". This test takes 10
clock cycles per word. For a Mini-ACE Mark3 with 4K words of
RAM, this is about 2.0 ms with a 20 MHz clock, 2.6 ms at 16
MHz, 3.4 ms at 12 MHz, or 4.1 ms at 10 MHz. For an Mini-ACE
Mark3 with 64K words of RAM, this test takes about 32.8 ms with
a 20 MHz clock, 40.1 ms at 16 MHz, 54.6 ms at 12 MHz, or 65.6
ms at 10 MHz.
The Mini-ACE Mark3 built-in protocol test is performed automati-
cally at power-up. In addition, the protocol or RAM self-tests may
be initiated by a command from the host processor, via the
START/RESET REGISTER. For RT mode, this may include the
host processor invoking self-test following receipt of an Initiate
self-test mode command. The results of the self-test are host
相关PDF资料 |
PDF描述 |
|---|---|
| A42MX36-2PQ100B | 40MX and 42MX FPGA Families |
| A42MX36-2PQ100ES | 40MX and 42MX FPGA Families |
| A42MX36-2TQ100 | 40MX and 42MX FPGA Families |
| A42MX36-2TQ100A | 40MX and 42MX FPGA Families |
| A42MX36-2TQ100B | 40MX and 42MX FPGA Families |
相关代理商/技术参数 |
参数描述 |
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