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参数资料
| 型号： | AD73522 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Dual Analog Front End with Flash based DSP Microcomputer(带闪速DSP微计算机的双模拟前端) |
| 中文描述： | 双模拟前端与闪存的DSP微机（带闪速DSP的微计算机的双模拟前端） |
| 文件页数： | 10/46页 |
| 文件大小： | 654K |
| 代理商： | AD73522 |
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AD73522
–10–
REV. PrC 05/99
Prelimnary Technical Data
SPORT Enable. Asynchronous input enable pin for the SPORT . When SE is set low by the DSP, the output pins
of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled internally in order to
decrease power dissipation. When SE is brought high, the control and data registers of the SPORT are at their
original values (before SE was brought low), however the timing counters and other internal registers are at their
reset values.
Analog Ground/Substrate Connection for Codec 1.
Analog Power Supply Connection for Codec 1.
Analog Output from the Positive T erminal of Output Channel 2.
Analog Output from the Negative T erminal of Output Channel 2.
Analog Output from the Positive T erminal of Output Channel 1.
Analog Output from the Negative T erminal of Output Channel1.
Analog Input to the inverting terminal of the inverting input amplifier on Channel 2's Positive Input.
Feedback connection from the output of the inverting amplifier on Channel 2's positive input. When the input
amplifiers are bypassed, this pin allows direct access to the positive input of Channel 2's sigma delta modulator.
Analog Input to the inverting terminal of the inverting input amplifier on Channel 2's Negative Input.
Feedback connection from the output of the inverting amplifier on Channel 2's negative input. When the input
amplifiers are bypassed, this pin allows direct access to the negative input of Channel 2's sigma delta modulator.
(Input) Processor Reset Input
(Input) Bus Request Input
(Output) Bus Grant Output
(Output) Bus Grant Hung Output
(Output) Data Memory Select Output
(Output) Program Memory Select Output
(Output) Memory Select Output
(Output) Byte Memory Select Output
(Output) Combined Memory Select Output
(Output) Memory Read Enable Output
(Output) Memory Write Enable Output
TECHNCAL
the negative edge of SCLK . SDI is ignored when SE is low.
PIN FUNC T ION DE SC RIPT ION
Mnemonic
Function
VINP1
VFBP1
Analog Input to the inverting terminal of the inverting input amplifier on Channel 1's Positive Input.
Feedback connection from the output of the inverting amplifier on Channel 1's positive input. When the input
amplifiers are bypassed, this pin allows direct access to the positive input of Channel 1's sigma delta modulator.
Analog Input to the inverting terminal of the inverting input amplifier on Channel 1's Negative Input.
Feedback connection from the output of the inverting amplifier on Channel 1's negative input. When the input
amplifiers are bypassed, this pin allows direct access to the negative input of Channel 1's sigma delta modulator.
Buffered Reference Output, which has a nominal value of 1.2 V.
A Bypass Capacitor to AGND2 of 0.1 μF is required for the on-chip reference. T he capacitor should be fixed to
this pin.
Analog Power Supply Connection for Codec 2.
Analog Ground/Substrate Connection for Codec 2.
Digital Ground/Substrate Connection.
Digital Power Supply Connection.
Active Low Reset Signal. T his input resets the entire chip, resetting the control registers and clearing the digital
circuitry.
Output Serial Clock whose rate determines the serial transfer rate to/from the codec. It is used to clock data or
control information to and from the serial port (SPORT ). T he frequency of SCLK is equal to the frequency of
the master clock (MCLK ) divided by an integer number—this integer number being the product of the external
master clock rate divider and the serial clock rate divider.
Master Clock Input. MCLK is driven from an external clock signal.
Serial Data Output of the Codec. Both data and control information may be output on this pin and is clocked on
the positive edge of SCLK . SDO is in three-state when no information is being transmitted and when SE is low.
Framing Signal Output for SDO Serial T ransfers. T he frame sync is one-bit wide and it is active one SCLK
period before the first bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK .
SDOFS is in three-state when SE is low.
Framing Signal Input for SDI Serial T ransfers. T he frame sync is one-bit wide and it is valid one SCLK period
before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of SCLK and is ignored
when SE is low.
Serial Data Input of the Codec. Both data and control information may be input on this pin and are clocked on
VINN1
VFBN1
REFOUT
REFC AP
AVDD2
AGND2
DGND
DVDD
RESET
SC L K
MC L K
SD O
SDOFS
SDIFS
SDI
SE
AGND1
AVDD1
VOUT P2
VOUT N2
VOUT P1
VOUT N1
VINP2
VFBP2
VINN2
VFBN2
RESET
BR
BG
BGH
D MS
PMS
IOMS
BMS
C MS
RD
WR
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