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参数资料
| 型号： | AD73522 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Dual Analog Front End with Flash based DSP Microcomputer(带闪速DSP微计算机的双模拟前端) |
| 中文描述： | 双模拟前端与闪存的DSP微机（带闪速DSP的微计算机的双模拟前端） |
| 文件页数： | 42/46页 |
| 文件大小： | 654K |
| 代理商： | AD73522 |
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AD73522
–42–
REV. PrC 05/99
Prelimnary Technical Data
PRELMNARY
DATA
delta modulator’s input section (SC PGA) is accessed
directly through the VFBP1 and VFBN1 pins for Channel
1 (VFBP2 and VFBN2 for C hannel 2).
It is also possible to drive the ADCs in either differential or
single-ended modes. If the single-ended mode is chosen it is
possible using software control to multiplex between two
single-ended inputs connected to the positive and negative
input pins.
T he primary concerns in interfacing to the ADC are firstly to
provide adequate anti-alias filtering and to ensure that the
signal source will drive the switched-capacitor input of the
ADC correctly. T he sigma-delta design of the ADC and its
over sampling characteristics simplify the antialias
requirements but it must be remembered that the single pole
RC filter is primarily intended to eliminate aliasing of
frequencies above the Nyquist frequency of the sigma-delta
modulator’s sampling rate (typically 2.048 MHz). It may
still require a more specific digital filter implementation in the
DSP to provide the final signal frequency response
characteristics. It is recommended that for optimum
performance that the capacitors used for the antialiasing filter
be of high quality dielectric (NPO). T he second issue
mentioned above is interfacing the signal source to the ADC’s
switched capacitor input load. T he SC input presents a
complex dynamic load to a signal source, therefore, it is
important to understand that the slew rate characteristic is an
important consideration when choosing external buffers for
use with the AD73522. T he internal inverting op amps on the
TECHNCAL
Amplifiers
T he AD73322’s ADC inputs are biased about the internal
reference level (REFCAP level), therefore it may be
necessary to either bias external signals to this level using
the buffered REFOUT level as the reference. T his is
applicable in either dc- or ac-coupled configurations. In the
case of dc coupling, the signal (biased to REFOUT ) may be
applied directly to the inputs (using amplifier bypass), as
shown in Figure 24, or it may be conditioned in an external
op amp where it can also be biased to the reference level
using the buffered REFOUT signal as shown in Figure 25
or it is possible to connect inputs directly to the AD73522’s
input op amps as shown in Figure 26.
VFBN1
GAIN
1
+6/15dB
PGA
COTIME
LOW-PASS
FILTER
V
REF
VINN
1
VINP1
VFBP1
VOUTP1
VOUTN1
REFOUT
REFERENCE
V
REF
ANTI-ALIAS
FILTER
100
V
0.047
m
F
0.047
m
F
100
V
REFCAP
0.1
m
F
0/38dB
PGA
Figure 24. Analog Input (DC-Coupled)
Analog Inputs
T here are several different ways in which the analog input
(encoder) section of the AD73522 can be interfaced to
external circuitry. It provides optional input amplifiers which
allows sources with high source impedance to drive the ADC
section correctly. When the input amplifiers are enabled, the
input channel is configured as a differential pair of inverting
amplifiers referenced to the internal reference (REFCAP)
level. T he inverting terminals of the input amplifier pair are
designated as pins VINP1 and VINN1 for Channel 1 (VINP2
and VINN2 for Channel 2) and the amplifier feedback
connections are available on pins VFBP1 and VFBN1 for
Channel 1 (VFBP2 and VFBN2 for Channel 2).
For applications where external signal buffering is required,
the input amplifiers can be bypassed and the ADC driven
directly. When the input amplifiers are disabled, the sigma-
AD73522’s AFE are specifically designed to interface to the
ADC’s SC input stage.
T he AD73522’s on-chip 38 dB preamplifier can be enabled
when there is not enough gain in the input circuit; the pream-
plifier is configured by bits IGS0-2 of CRD. T he total gain
must be configured to ensure that a full-scale input signal
produces a signal level at the input to the sigma-delta
modulator of the ADC that does not exceed the maximum
input range.
T he dc biasing of the analog input signal is accomplished with
an on-chip voltage reference. If the input signal is not biased
at the internal reference level (via REFOUT ), then it must
be ac-coupled with external coupling capacitors. C
IN
should
accomplished using resistors to REFOUT as in Figures 31
and 32.
VFBN1
GAIN
1
+6/15dB
PGA
CONTINUOUS
TIME
LOW-PASS
FILTER
V
REF
1
VINP1
VFBP1
VOUTP1
VOUTN1
REFCAP
REFOUT
REFERENCE
0/38dB
PGA
V
REF
OPTIONAL
BUFFER
ANTI-ALIAS
FILTER
0.1
m
F
100
V
0.047
100
V
m
F
0.047
m
F
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