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| 型号： | AD73522 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Dual Analog Front End with Flash based DSP Microcomputer(带闪速DSP微计算机的双模拟前端) |
| 中文描述： | 双模拟前端与闪存的DSP微机（带闪速DSP的微计算机的双模拟前端） |
| 文件页数： | 30/46页 |
| 文件大小： | 654K |
| 代理商： | AD73522 |
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AD73522
–30–
REV. PrC 05/99
Prelimnary Technical Data
PRELMNARY
DATA
Not Applicable Not Applicable
0
13 LSBs of Ad-
TECHNCAL
external memory space while using a different external
memory space for BDMA transfers during normal operation.
You can use the
CMS
to select the first external memory
space for BDMA transfers and
BMS
to select the second
external memory space for booting. T he
BMS
signal can be
disabled by setting Bit 3 of the System Control Register to 1.
T he System Control Register is illustrated in Figure 17.
D AT A ME MORY
Data Memory (Full Memory Mode)
is a 16-bit-wide space
used for the storage of data variables and for memory-mapped
control registers. T he AD73522-80 has 16K words on Data
Memory RAM on chip (the AD73522-40 has 8K words on
Data Memory RAM on chip), consisting of 16,352 user-
accessible locations in the case of the AD73522-80 ( 8,160
user-accessible locations in the case of the AD73522-40) and
32 memory-mapped registers. Support also exists for up to
two 8K external memory overlay spaces through the external
data bus. All internal accesses complete in one cycle. Accesses
to external memory are timed using the wait states specified
by the DWAIT register.
ACCESSIBLE WHEN
ACCESSIBLE WHEN
32 MEMORY
MAPPED
REGISTERS
0
x
3FFF
0
x
2000
0
x
1FFF
INTERNAL
8160
WORDS
0
x
0000
DATA MEMORY
ADDRESS
AALWAYS
0
x
2
000 0
x
3
FFF
ADMOVLAY = 01
INTERNAL
EXTERNAL
0
x
0000-
0
x
1FFF
0
x
0000-
0
x
1FFF
0
x
0000-
0
x
1FFF
DATA MEMORY
8K INTERNAL
DMOVLAY = 01
OR
EXTERNAL 8K
0
x
3FE0
0
x
3FDF
1NOT ACCESSIBLE ON AD73422-40
Figure 16. Data Memory Map
Data Memory (Host Mode) allows access to all internal
memory. External overlay access is limited by a single external
address line (A0). T he DMOVLAY bits are defined in T able
X X II.
T able X X II. DMOVLAY Bits
DMOVLAY
Memory
A13
A12:0
0,
1
dress
Internal
External
Overlay 1
Between 0x2000
and 0x3FFF
13 LSBs of Ad-
2
dress
External
1
Overlay 2
Between 0x2000
and 0x3FFF
I/O Space (F ull Memory Mode)
T he AD73522 supports an additional external memory space
called I/O space. T his space is designed to support simple
connections to peripherals (such as data converters and
external registers) or to bus interface ASIC data registers. I/O
space supports 2048 locations of 16-bit wide data. T he lower
eleven bits of the external address bus are used; the upper
three bits are undefined. T wo instructions were added to the
core ADSP-2100 Family instruction set to read from and
write to I/O memory space. T he I/O space also has four dedi-
cated 3-bit wait state registers, IOWAIT 0-3, that specify up
to seven wait states to be automatically generated for each of
four regions. T he wait states act on address ranges as shown
in T able X X III.
T able X X III. Wait States
Address Range
0x000–0x1FF
0x200–0x3FF
0x400–0x5FF
0x600–0x7FF
Wait State Register
IOWAIT 0
IOWAIT 1
IOWAIT 2
IOWAIT 3
C omposite Memory Select (
T he AD73522 has a programmable memory select signal that
is useful for generating memory select signals for memories
mapped to more than one space. T he
CMS
signal is gener-
ated to have the same timing as each of the individual
memory select signals (
PMS
,
DMS
,
BMS
,
IOMS
) but can
functionality.
Each bit in the CMSSEL register, when set, causes the
CMS
signal to be asserted when the selected memory select is as-
serted. For example, to use a 32K word memory to act as
both program and data memory, set the
PMS
and
DMS
bits
in the CMSSEL register and use the
CMS
pin to drive the
chip select of the memory; use either
DMS
or
PMS
as the
additional
address bit.
T he
CMS
pin functions like the other memory select signals,
bit causes the assertion of the
CMS
signal at the same time as
the selected memory select signal. All enable bits default to 1
at reset, except the
BMS
bit.
) Disable
T he AD73522 also lets you boot the processor from one
CMS
)
Boot Memory Select (
BMS
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DM (0
3
3FFF)
SY STEM CONTROL REGISTER
SPORT0 ENABLE
1 = ENABLED, 0 = DISABLED
SPORT1 ENABLE
1 = ENABLED, 0 = DISABLED
SPORT1 CONFIGURE
1 = SERIAL PORT
0 = F1, FO,
IRQ0
,
IRQ1
, SCLK
PWAIT
PROGRAM MEMORY
WAIT STATES
B M S
ENABLE
0 = ENABLED, 1 = DISABLED
Figure 17. System Control Register
Byte Memory
T he byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory
is accessed using the BDMA feature. T he BDMA Control
Register is shown in Figure 18. T he byte memory space con-
sists of 256 pages, each of which is 16K
∞
8.
T he byte memory space on the AD73522 supports read and
write operations as well as four different data formats. T he
byte memory uses data bits 15:8 for data. T he byte memory
uses data bits 23:16 and address bits 13:0 to create a 22-bit
address. T his allows up to a 4 meg
∞
8 (32 megabit) ROM or
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