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| 型号： | AD73522 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Dual Analog Front End with Flash based DSP Microcomputer(带闪速DSP微计算机的双模拟前端) |
| 中文描述： | 双模拟前端与闪存的DSP微机（带闪速DSP的微计算机的双模拟前端） |
| 文件页数： | 31/46页 |
| 文件大小： | 654K |
| 代理商： | AD73522 |
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AD73522
–31–
REV. PrC 05/99
Prelimnary Technical Data
PRELMNARY
DATA
Unused bits in the 8-bit data memory formats are filled with
0s. T he BIAD register field is used to specify the starting
address for the on-chip memory involved with the transfer.
T he 14-bit BEAD register specifies the starting address for
the external byte memory space. T he 8-bit BMPAGE register
specifies the starting page for the external byte memory space.
T he BDIR register field selects the direction of the transfer.
Finally the 14-bit BWCOUNT register specifies the number
of DSP words to transfer and initiates the BDMA circuit
transfers.
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the
completion of the number of transfers specified by the
BWC OUNT
register.
T he BWCOUNT register is updated after each transfer so it
can be used to check the status of the transfers. When it
reaches zero, the transfers have finished and a BDMA
interrupt is generated. T he BMPAGE and BEAD registers
must not be accessed by the DSP during BDMA operations.
T he source or destination of a BDMA transfer will always be
on-chip program or data memory.
When the BWCOUNT register is written with a nonzero
value, the BDMA circuit starts executing byte memory
accesses with wait states set by BMWAIT . T hese accesses
continue until the count reaches zero. When enough accesses
TECHNCAL
L SBs
RAM to be used without glue logic. All byte memory accesses
are timed by the BMWAIT register.
Byte Memory DMA (BDMA, F ull Memory Mode)
T he Byte memory DMA controller allows loading and storing
of program instructions and data using the byte memory
space. T he BDMA circuit is able to access the byte memory
space while the processor is operating normally, and steals
only one DSP cycle per 8-, 16- or 24-bit word transferred.
BDMA CONTROL
9
8
BMPAGE
BDMA
OVERLAY
BTY PE
0 = LOAD FROM BM
1 = STORE TO BM
BCR
0 = RUN DURING BDMA
1 = HALT DURING BDMA
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
5
1
4
1
3
1
2
1
1
1
0
7
6
5
4
3
2
1
0
DM
(0
3
3FE3)
Figure 18. BDMA Control Register
T he BDMA circuit supports four different data formats that
are selected by the BT YPE register field. T he appropriate
number of 8-bit accesses are done from the byte memory
space to build the word size selected. T able X X IV shows the
data formats supported by the BDMA circuit.
T able X X IV. Data Formats
Internal
Memory Space
BTYPE
Word Size
Alignment
00
01
10
11
Program Memory
Data Memory
Data Memory
Data Memory
24
16
8
8
Full Word
Full Word
MSBs
have occurred to create a destination word, it is transferred to
or from on-chip memory. T he transfer takes one DSP cycle.
DSP accesses to external memory have priority over BDMA
byte memory accesses.
T he BDMA Context Reset bit (BCR) controls whether or not
the processor is held off while the BDMA accesses are occur-
ring. Setting the BCR bit to 0 allows the processor to
continue operations. Setting the BCR bit to 1 causes the
processor to stop execution while the BDMA accesses are
occurring, to clear the context of the processor and start
execution at address 0 when the BDMA accesses have
completed.
T he BDMA overlay bits specify the OVLAY memory blocks
Internal Memory D MA Port (ID MA Port; H ost Memory
Mode)
T he IDMA Port provides an efficient means of
communication between a host system and the AD73522.
T he port is used to access the on-chip program memory and
data memory of the DSP with only one DSP cycle per word
overhead. T he IDMA port cannot be used, however, to write
to the DSP’s memory-mapped control registers. A typical
IDMA transfer process is described as follows:
1. Host starts IDMA transfer.
2. Host checks
control line to see if the DSP is busy.
3. Host uses
IS
and IAL control lines to latch either the
DMA starting address (IDMAA) or the PM/DM OVLAY
selection into the DSP’s IDMA control registers.
If IAD[15] = 1, the value of IAD[7:0] represent the IDMA
overlay: IAD[14:8] must be set to 0.
If IAD[15] = 0, the value of IAD[13:0] represent the
starting address of internal memory to be accessed and
IAD[14] reflects PM or DM for access.
4. Host uses
IS
and
IRD
(or
IWR
) to read (or write) DSP
internal memory (PM or DM).
5. Host checks IACK line to see if the DSP has completed
the previous IDMA operation.
6. Host ends IDMA transfer.
T he IDMA port has a 16-bit multiplexed address and data
bus and supports 24-bit program memory. T he IDMA port
is
completely asynchronous and can be written to while the
AD73522 is operating at full speed.
T he DSP memory address is latched and then automatically
incremented after each IDMA transaction. An external device
can therefore access a block of sequentially addressed memory
by specifying only the starting address of the block. T his in-
creases throughput as the address does not have to be sent for
each memory access.
IDMA Port access occurs in two phases. T he first is the
IDMA Address L atch cycle. When the acknowledge is
asserted, a
14-bit address and 1-bit destination type can be driven onto
the bus by an external device. T he address specifies an on-
chip memory location; the destination type specifies whether
it is a DM or PM access. T he falling edge of the address latch
signal latches this value into the IDMAA register.
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