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| 型号： | AD73522 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Dual Analog Front End with Flash based DSP Microcomputer(带闪速DSP微计算机的双模拟前端) |
| 中文描述： | 双模拟前端与闪存的DSP微机（带闪速DSP的微计算机的双模拟前端） |
| 文件页数： | 34/46页 |
| 文件大小： | 654K |
| 代理商： | AD73522 |
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AD73522
–34–
REV. PrC 05/99
Prelimnary Technical Data
PRELMNARY
DATA
For your target system to be compatible with the EZ-ICE
emulator, it must comply with the memory interface
guidelines listed below.
PM, D M, BM, IOM and C M
Design your Program Memory (PM), Data Memory (DM),
Byte Memory (BM), I/O Memory (IOM) and Composite
Memory (CM) external interfaces to comply with worst case
device timing requirements and switching characteristics as
specified in the DSP’s data sheet. T he performance of the
EZ-ICE
may approach published worst case specification for
some memory access timing requirements and switching
characteristics.
Note:
If your target does not meet the worst case chip specifi-
cation for memory access parameters, you may not be able to
emulate your circuitry at the desired CLK IN frequency. De-
pending on the severity of the specification violation, you may
have trouble manufacturing your system as DSP components
statistically vary in switching characteristic and timing require-
ments within published limits.
Restriction:
All memory strobe signals on the AD73522 (
RD
,
WR
,
PMS
,
DMS
,
BMS
,
CMS
and
IOMS
) used in your target
system must have 10 k
pull-up resistors connected when the
EZ-ICE is being used. T he pull-up resistors are necessary
because there are no internal pull-ups to guarantee their state
during prolonged three-state conditions resulting from typical
EZ-ICE debugging sessions. T hese resistors may be removed
at your option when the EZ-ICE is not being used.
TECHNCAL
T arget Board C onnector for E Z-IC E Probe
T he EZ-ICE connector (a standard pin strip header) is shown
in Figure 21. You must add this connector to your target
board design if you intend to use the EZ-ICE. Be sure to
allow enough room in your system to fit the EZ-ICE probe
onto the 14-pin connector.
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
GND
K EY (NO PIN)
RESET
BR
BG
TOP VIEW
EBG
EBR
ELOUT
EE
EINT
ELIN
ECLK
EMS
ERESET
Figure 21. Target Board Connector for EZ-ICE
T he 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-
tion—you must remove Pin 7 from the header. T he pins must
be 0.025 inch square and at least 0.20 inch in length. Pin
spacing should be 0.1 x 0.1 inches. T he pin strip header must
have at least 0.15 inch clearance on all sides to accept the EZ-
ICE probe plug.
Pin strip headers are available from vendors such as 3M,
McK enzie and Samtec.
T arget Memory Interface
T arget System Interface Signals
When the EZ-ICE
board is installed, the performance on
some system signals changes. Design your system to be com-
patible with the following system interface signal changes
introduced by the EZ-ICE
board:
EZ-ICE
emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the
RESET
signal.
EZ-ICE
emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the
BR
signal.
EZ-ICE
emulation ignores RESET and BR when single-
stepping.
EZ-ICE
emulation ignores
RESET
and
BR
when in Emula-
tor Space (DSP halted).
EZ-ICE
emulation ignores the state of target
BR
in certain
modes. As a result, the target system may take control of
the DSP’s external memory bus
only
if bus grant (BG) is
asserted by the EZ-ICE
board’s DSP.
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