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参数资料
| 型号： | AD73522 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Dual Analog Front End with Flash based DSP Microcomputer(带闪速DSP微计算机的双模拟前端) |
| 中文描述： | 双模拟前端与闪存的DSP微机（带闪速DSP的微计算机的双模拟前端） |
| 文件页数： | 41/46页 |
| 文件大小： | 654K |
| 代理商： | AD73522 |
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AD73522
–41–
REV. PrC 05/99
Prelimnary Technical Data
DATA
RESETC
TECHNCAL
SDOFS
ANAL OG F RONT E ND (AF E ) INT E RF AC ING
T he AFE section of the AD73522 features two voiceband
input/output channels, each with 16-bit linear resolution.
Connectivity to the AFE section from the DSP is
uncommitted thus allowing the user the flexibility of
connecting in the mode or configuration of their choice. T his
section will detail several configurations - with no extra AFE
channels configured and with two extra AFE channels
configured (using an external AD73322 dual AFE).
DSP SPORT to AF E Interfacing
T he SCLK , SDO, SDOFS, SDI and SDIFS pins of
SPORT 2 must be connected to the Serial Clock, Receive
Data, Receive Data Frame Sync, T ransmit Data and
T ransmit Data Frame Sync pins respectively of either
SPORT 0 or SPORT 1.. T he SE pin may be controlled from a
parallel output pin or flag pin such as FL0-2 or, where
SPORT 2 powerdown is not required, it can be permanently
strapped high using a suitable pull-up resistor. T he RESET C
pin may be connected to the system hardware reset structure
or it may also be controlled using a dedicated control line. In
the event of tying it to the global system reset, it is advisable
to operate the device in mixed mode, which allows a
software reset, otherwise there is no convenient way of
resetting the AFE section.
TFS
DT
SCLK
DR
RFS
DSP
SECTION
AFE
SECTION
SDIFS
SDI
SCLK
SDO
FL0
FL1
SE
Figure 21. AD73522 AFE to DSP Connection
C ascade Operation
Where it is required to configure extra analog I/O channels to
the existing two channels on the AD73522, it is possible to
cascade up to 6 more channels (using single channel
AD73311 or dual channel AD73322 AFEs) by using the
scheme described in Figure 23. It is necessary however to
ensure that the timing of the SE and RESET signals is syn-
chronized at each device in the cascade. A simple D type flip
flop is sufficient to sync each signal to the master clock
MCLK , as in Figure 22.
1/2
74HC74
CLK
D
Q
DSP CONTROL
TO SE
MCLK
SE SIGNAL SYNCHRONIZED
TO MCLK
1/2
74HC74
CLK
D
Q
DSP CONTROL
TO
RESET
MCLK
RESET
SIGNAL SYNCHRONIZED
TO MCLK
Figure 22. SE and
RESET
Sync Circuit for Cascaded
Operation
Connection of a cascade of devices to a DSP, as shown in
Figure 23, is no more complicated than connecting a single
device. Instead of connecting the SDO and SDOFS to the
DSP’s Rx port, these are now daisy-chained to the SDI and
SDIFS of the next device in the cascade. T he SDO and
SDOFS of the final device in the cascade are connected to
the DSP section’s Rx port to complete the cascade. SE and
RESET on all devices are fed from the signals that were
synchronized with the MCLK using the circuit as described
above. T he SCLK from only one device need be connected
to the DSP section’s SCLK input(s) as all devices will be
running at the same SCLK frequency and phase.
TFS
DT
DR
RFS
AFE
SECTION
SDIFS
SDI
SCLK
SDO
SDOFS
SCLK
DEVICE 1
MCLK
SE
RESET
ADDITIONAL
AD73322
CODEC
SDIFS
SDI
SCLK
SDO
SDOFS
DEVICE 2
MCLK
SE
RESET
74HC74
Q1
Q2
D1
D2
FL0
FL1
DSP
SECTION
Figure 23. Connection of an AD73322 Cascaded to
AD73522
Interfacing to the AF E ’s analog inputs and outputs
T he AFE section of the AD73522 offers a flexible interface
for microphone pickups, line level signals or PST N line
intefaces. T his section will detail some of the configurations
that can be used with the input and output sections.
T he AD73322 features both differential inputs and outputs
on each channel to provide optimal performance and avoid
common mode noise. It is also possible to interface either
inputs or outputs in single-ended mode. T his section details
the choice of input and output configurations and also gives
some tips towards successful configuration of the analog
interface sections.
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