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| 型号： | AD73522 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Dual Analog Front End with Flash based DSP Microcomputer(带闪速DSP微计算机的双模拟前端) |
| 中文描述： | 双模拟前端与闪存的DSP微机（带闪速DSP的微计算机的双模拟前端） |
| 文件页数： | 26/46页 |
| 文件大小： | 654K |
| 代理商： | AD73522 |
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AD73522
–26–
REV. PrC 05/99
Prelimnary Technical Data
PRELMNARY
DATA
TECHNCAL
IMASK register. T his does not affect serial port auto-
buffering or DMA transfers.
T he interrupt control register, ICNT L, controls interrupt
nesting and defines the
IRQ0
,
IRQ1
and
IRQ2
external inter-
rupts to be either edge- or level-sensitive. T he
IRQE
pin is an
external edge-sensitive interrupt and can be forced and
cleared. T he
IRQL0
and
IRQL1
pins are external level-sensi-
tive interrupts.
T he IFC register is a write-only register used to force and
clear interrupts. On-chip stacks preserve the processor status
and are automatically maintained during interrupt handling.
T he stacks are twelve levels deep to allow interrupt, loop and
subroutine nesting. T he following instructions allow global
enable or disable servicing of the interrupts (including power
down), regardless of the state of IMASK . Disabling the
interrupts does not affect serial port autobuffering or DMA.
ENA INTS;
DIS INTS;
When the processor is reset, interrupt servicing is enabled.
Pin T erminations (Continued)
I/O
3-State
(Z)
Hi-Z*
C aused
By
Pin
Name
Reset
State
Unused
C onfiguration
WR
B R
B G
B G H
IR Q2/PF 7
O (Z)
I
O (Z)
O
I/O (Z)
O
I
O
O
I
BR, E BR F loat
High (Inactive)
F loat
F loat
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High (Inactive)
or Program as Output,
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High or Low,
Output = Float
High or Low
High or Low
High or Low
F loat
Input = High or Low,
Output = Float
High or Low
High or Low
High or Low
F loat
E E
IR QL 1/PF 6 I/O (Z)
I
IR QL 0/PF 5 I/O (Z)
I
IR QE /PF 4
I/O (Z)
I
SC L K 0
I/O
I
R F S0
D R 0
T F S0
D T 0
SC L K 1
I/O
I
I/O
O
I/O
I
I
O
O
I
R F S1/R Q0
D R 1/F I
T F S1/R Q1
D T 1/F O
E E
E B R
E B G
E R E SE T
E MS
E INT
E C L K
E L IN
E L OUT
I/O
I
I/O
O
I
I
O
I
O
I
I
I
O
I
I
O
O
I
I
O
I
O
I
I
I
O
NOT ES
*
*Hi-Z = High Impedance.
1.If the CLK OUT pin is not used, turn it OFF.
2.If the Interrupt/Programmable Flag pins are not used, there are two options:
Option 1: When these pins are configured as INPUT S at reset and function as
interrupts and input flag pins, pull the pins High (inactive).
Option 2: Program the unused pins as OUT PUT S, set them to 1, and let them
float.
3.All bidirectional pins have three-stated outputs. When the pins is configured as
an output, the output is Hi-Z (high impedance) when inactive.
4.CLK IN, RESET , and PF3:0 are not included in the table because these pins
must be used.
Interrupts
T he interrupt controller allows the processor to respond to the
eleven possible interrupts and
RESET
with minimum overhead.
T he AD73522 provides four dedicated external interrupt
input pins,
IRQ2
,
IRQL0
,
IRQL1
and
IRQE
. In addition,
SPORT 1 may be reconfigured for
IRQ0
,
IRQ1
, FLAG_IN and
FLAG_OUT , for a total of six external interrupts. T he
AD73522 also supports internal interrupts from the timer, the
byte DMA port, the two serial ports, software and the power-
down control circuit. T he interrupt levels are internally
prioritized and individually maskable (except power down and
reset). T he
IRQ2
,
IRQ0
and
IRQ1
input pins can be pro-
grammed to be
either level- or edge-sensitive.
IRQL0
and
IRQL1
are level-
sensitive and
IRQE
is edge sensitive. T he priorities and vector
addresses of all interrupts are shown in T able X IX .
T able X IX . Interrupt Priority and Interrupt Vector Ad-
dresses
Interrupt Vector
Address (Hex)
Source of Interrupt
RESET
(or Power-Up with PUCR = 1) 0000 (
Highest Priority
)
Power-Down (Nonmaskable)
IRQ2
IRQL1
IRQL0
SPORT 0 T ransmit
SPORT 0 Receive
IRQE
BDMA Interrupt
SPORT 1 T ransmit or IRQ1
SPORT 1 Receive or IRQ0
T imer
002C
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028 (
Lowest Priority
)
Individual interrupt requests are logically ANDed with the
bits in IMASK ; the highest priority unmasked interrupt is
then selected. T he power-down interrupt is nonmaskable.
T he AD73522 masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
L OW POWE R OPE RAT ION
T he AD73522 has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. T hese modes are:
Power-Down
Idle
Slow Idle
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