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| 型号： | AD73522 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Dual Analog Front End with Flash based DSP Microcomputer(带闪速DSP微计算机的双模拟前端) |
| 中文描述： | 双模拟前端与闪存的DSP微机（带闪速DSP的微计算机的双模拟前端） |
| 文件页数： | 27/46页 |
| 文件大小： | 654K |
| 代理商： | AD73522 |
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AD73522
–27–
REV. PrC 05/99
Prelimnary Technical Data
Power-down acknowledge pin indicates when the processor
has entered power-down.
Idle
When the AD73522 is in the Idle Mode, the processor waits
indefinitely in a low power state until an interrupt occurs.
When an unmasked interrupt occurs, it is serviced; execution
then continues with the instruction following the
IDLE
instruction. In Idle Mode IDMA, BDMA and autobuffer cycle
steals still occur.
TECHNCAL
T he CLK OUT pin may also be disabled to reduce external
power dissipation.
Power-D own
T he AD73522 processor has a low power feature that lets the
processor enter a very low power dormant state through hard-
ware or software control. Here is a brief list of power-down
features. Refer to the
ADSP-2100 Family User’s Manual
, T hird
Edition, “System Interface” chapter, for detailed information
about the power-down feature.
Quick recovery from power-down. T he processor begins
executing instructions in as few as 400 CLK IN cycles.
Support for an externally generated T T L or CMOS proces-
sor clock. T he external clock can continue running during
power-down without affecting the 400 CLK IN cycle recov-
ery.
Support for crystal operation includes disabling the oscilla-
tor to save power (the processor automatically waits 4096
CLK IN cycles for the crystal oscillator to start and stabi-
lize), and letting the oscillator run to allow 400 CLK IN
cycle start up.
Power-down is initiated by either the power-down pin
(
PWD
) or the software power-down force bit Interrupt
support allows an unlimited number of instructions to be
executed before optionally powering down. T he power-
down interrupt also can be used as a non-maskable, edge-
sensitive interrupt.
Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving
the power-down state.
T he
RESET
pin also can be used to terminate power-
down.
Slow Idle
T he
IDLE
instruction on the AD73522 slows the processor’s
internal clock signal, further reducing power consumption.
T he reduced clock frequency, a programmable fraction of the
normal clock rate, is specified by a selectable divisor given in
the
IDLE
instruction. T he format of the instruction is
IDLE (n);
where
n
= 16, 32, 64 or 128. T his instruction keeps the pro-
cessor fully functional, but operating at the slower clock rate.
While it is in this state, the processor’s other internal clock
signals, such as SCLK , CLK OUT and timer clock, are re-
duced by the same ratio. T he default form of the instruction,
when no clock divisor is given, is the standard
IDLE
instruc-
tion.
When the
IDLE (n)
instruction is used, it effectively slows
down the processor’s internal clock and thus its response time
to incoming interrupts. T he one-cycle response time of the
standard idle state is increased by
n
, the clock divisor. When
an enabled interrupt is received, the AD73522 will remain in
the idle state for up to a maximum of
n
processor cycles (
n
=
16, 32, 64 or 128) before resuming normal operation.
When the
IDLE (n)
instruction is used in systems that have
an externally generated serial clock (SCLK ), the serial clock
rate may be faster than the processor’s reduced internal clock
rate. Under these conditions, interrupts must not be
generated at a faster rate than can be serviced, due to the
additional time the processor takes to come out of the idle
state (a maximum of
n
processor cycles).
SY ST E M INT E RF AC E
Figure 13 shows a typical basic system configuration with the
AD73522, two serial devices, a byte-wide EPROM, and
optional external program and data overlay memories (mode
selectable). Programmable wait state generation allows the
processor to connect easily to slow peripheral devices. T he
AD73522 also provides four external interrupts and two serial
ports or six external interrupts and one serial port. Host
Memory Mode allows access to the full external data bus, but
limits addressing to a single address bit (A0) Additional
system peripherals can be added in this mode through the use
of external hardware to generate and latch address signals.
C lock Signals
T he AD73522 can be clocked by either a crystal or a T T L-
compatible clock signal.
T he CLK IN input cannot be halted, changed during
operation or operated below the specified frequency during
normal operation. T he only exception is while the processor is
in the power-down state. For additional information, refer
to Chapter 9,
ADSP-2100 Family User’s Manual, Third Edition,
for detailed information on this power-down feature.
If an external clock is used, it should be a T T L-compatible
signal running at half the instruction rate. T he signal is con-
nected to the processor’s CLK IN input. When an external
clock is used, the X T AL input must be left unconnected.
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