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| 型号： | AD73522 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Dual Analog Front End with Flash based DSP Microcomputer(带闪速DSP微计算机的双模拟前端) |
| 中文描述： | 双模拟前端与闪存的DSP微机（带闪速DSP的微计算机的双模拟前端） |
| 文件页数： | 22/46页 |
| 文件大小： | 654K |
| 代理商： | AD73522 |
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AD73522
–22–
REV. PrC 05/99
Prelimnary Technical Data
DATA
DAC channel as the reconstructed output signal can be
monitored using the ADC as a sampler. Analog Loop-Back is
enabled by setting the ALB bit (CRF:7)
NOT E: Analog Loop-Back can only be enabled if the Analog
Gain T ap is powered-down (CRC:1 = 0).
TECHNCAL
output events occur simultaneously and is the simplest
configuration for operation in normal Data Mode. Note that
when programming the DSP in this configuration it is
advisable to preload the T x register with the first control word
to be sent before the codec is taken out of reset. T his ensures
that this word will be transmitted to coincide with the first
output word from the device(s).
the data. Note that the output samples from the ADC will
also have the MSB set to zero to indicate it is a data word.
A description of a single device operating in mixed mode is
detailed in Appendix B, while Appendix D details the initial-
ization and operation of a dual codec cascade operating in
mixed mode. Note that it is not essential to load the control
registers in Program Mode before setting mixed mode active.
It is also possible to initiate mixed mode by programming
CRA with the first control word and then interleaving control
words with DAC data.
Digital L oop-Back
T his mode can be used for diagnostic purposes and allows the
user to feed the ADC samples from the ADC register directly
to the DAC register. T his forms a loop-back of the analog
input to the analog output by reconstructing the encoded
signal using the decoder channel. T he serial interface will
continue to work, which allows the user to control gain
settings, etc. Only when DLB is enabled with mixed mode
operation can the user disable the DLB, otherwise the device
must be reset.
SPORT L oop-Back
T his mode allows the user to verify the DSP interfacing and
connection by writing words to the SPORT of the devices
and have them returned back unchanged after a delay of 16
SCLK cycles. T he frame sync and data word that are sent to
the device are returned via the output port. Again, SLB mode
can only be disabled when used in conjunction with mixed
mode, otherwise the device must be reset.
Analog L oop-Back
In Analog Loop-Back mode, the differential DAC output is
connected, via a loopback switch, to the ADC input. T his
mode allows the ADC channel to check functionality of the
Gain
+/- 1
VINN1
VINP1
VFBN1
VFBP1
VREF
VOUTP1
VOUTN1
Continuous
Time
Low-Pass
Filter
+6/-15dB
PGA
VREF
AD73422
AFE
SECTION
Analog
Loopback
Enabled
Single-Ended
Enable
Invert
Inverting Op-
amps
Analog Gain
Tap powered
Down
0/38 dB
PGA
REFOUT
REFCAP
Reference
Figure 9. Analog Loop-Back Connectivity
AF E INT E RF AC ING
T he AFE section SPORT (SPORT 2) can be interfaced to
either SPORT 0 or SPORT 1 of the DSP section. Both serial
input and output data use an accompanying frame
synchronization signal which is active high one clock cycle
before the start of the 16-bit word or during the last bit of the
previous word if transmission is continuous. T he serial clock
(SCLK ) is an output from the codec and is used to define the
serial transfer rate to the DSP’s T x and Rx ports. T wo primary
configurations can be used: the first is shown in Figure 10
where the DSP’s T x data, T x frame sync, Rx data and Rx
frame sync are connected to the codec’s SDI, SDIFS, SDO
and SDOFS respectively. T his configuration, referred to as
indirectly coupled or non frame sync loop-back, has the effect
of decoupling the transmission of input data from the receipt
of output data. T he delay between receipt of codec output
data and transmission of input data for the codec is
determined by the DSP’s software latency. When
programming the DSP serial port for this con-
figuration, it is necessary to set the Rx FS as an input and the
T x FS as an output generated by the DSP. T his configuration
is most useful when operating in mixed mode, as the DSP has
the ability to decide how many words (either DAC or control)
can be sent to the codecs. T his means that full control can be
implemented over the device configuration as well as updating
the DAC in a given sample interval. T he second configura-
tion (shown in Figure 11) has the DSP’s T x data and Rx data
connected to the codec’s SDI and SDO, respectively while
the DSP’s T x and Rx frame syncs are connected to the
codec’s SDIFS and SDOFS. In this configuration, referred to
signals are connected together and the input data to the
codec is forced to be synchronous with the output data from
the codec. T he DSP must be programmed so that both the
T x FS and Rx FS are inputs as the codec SDOFS will be
input to both. T his configuration guarantees that input and
AFE
SECTION
SDIFS
SDI
SCLK2
SDO
SDOFS
TFS(0/1)
DT(0/1)
SCLK(0/1)
DR(0/1)
RFS(0/1)
DSP
SECTION
CHANNEL 1
CHANNEL 2
AD73422
Figure 10. Indirectly Coupled or Non Frame Sync Loop-
Back Configuration
C ascade Operation
T he AD73522 has been designed to support cascading of
extra external AFEs from either SPORT 0 or SPORT 1.
Cascaded operation can support mixes of dual or single
channel devices with maximum number of codec units being
eight (the AD73522 has two codec units configured on the
device). T he SPORT 2 interface protocol has been designed
so that device addressing is built into the packet of
information sent to the device. T his allows the cascade to be
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