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| 型号： | AD73522 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Dual Analog Front End with Flash based DSP Microcomputer(带闪速DSP微计算机的双模拟前端) |
| 中文描述： | 双模拟前端与闪存的DSP微机（带闪速DSP的微计算机的双模拟前端） |
| 文件页数： | 32/46页 |
| 文件大小： | 654K |
| 代理商： | AD73522 |
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AD73522
–32–
REV. PrC 05/99
Prelimnary Technical Data
DATA
DESTINATION MEMORY TYPE:
0 = PM
1 = DM
TECHNCAL
instruction does not need to be completed when the bus is
granted. If a single instruction requires two external memory
accesses, the bus will be granted between the two accesses.
When the
BR
signal is released, the processor releases the
BG
signal, reenables the output drivers and continues program
execution from the point at which it stopped.
T he bus request feature operates at all times, including when
the processor is booting and when
RESET
is active.
T he
BGH
pin is asserted when the AD73522 is ready to ex-
ecute an instruction, but is stopped because the external bus
is already granted to another device. T he other device can
release the bus by deasserting bus request. Once the bus is
released, the AD73522 deasserts
BG
and
BGH
and executes
the external memory access.
Once the address is stored, data can either be read from or
written to the AD73522’s on-chip memory. Asserting the
select line (
IS
) and the appropriate read or write line (
IRD
and
IWR
respectively) signals the AD73522 that a particular
transaction is required. In either case, there is a one-
processor-cycle delay for synchronization. T he memory access
consumes one additional processor cycle.
Once an access has occurred, the latched address is automati-
cally incremented and another access can occur.
T hrough the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation.
Asserting the IDMA port select (
IS
) and address latch enable
(IAL) directs the AD73522 to write the address onto the
IAD0–14 bus into the IDMA C ontrol Register. If IAD[15]
is set to 0, IDMA latches the address. If IAD[15] is set to
1, IDMA latches OVLAY memory. T he IDMA OVLAY and
address are stored in separate memory-mapped registers. T he
IDMAA register, shown below, is memory mapped at address
DM (0x3FE0). Note that the latched address (IDMAA)
cannot be read back by the host. T he IDMA OVL AY register
is memory mapped at address DM (0x3FE7). See Figure 19
for more information on IDMA and DMA memory maps.
IDMA CONTROL (U = UNDEFINED AT RESET)
DM(0
3
3FE0)
IDMAA
ADDRESS
IDMAD
U
3
0
U U
U U U U
U
1
5
1
4
1
1
2
1
1
1
9
8
7
6
5
4
3
2
1
0
Figure 19. IDMA Control/OVLAY Registers
Bootstrap L oading (Booting)
T he AD73522 has two mechanisms to allow automatic load-
ing of the internal program memory after reset. T he method
for booting after reset is controlled by the Mode A, B and C
configuration bits.
When the mode pins specify BDMA booting, the AD73522
initiates a BDMA boot sequence when reset is released.
T he BDMA interface is set up during reset to the following
defaults when BDMA booting is specified: the BDIR,
BMPAGE, BIAD and BEAD registers are set to 0, the
BT YPE register is set to 0 to specify program memory 24-
bit words, and the BWCOUNT register is set to 32. T his
causes 32 words of on-chip program memory to be loaded
from byte memory. T hese 32 words are used to set up the
BDMA to load in the remaining program code. T he BCR bit
is also set to 1, which causes program execution to be held off
until all 32 words are loaded into on-chip program memory.
Execution then begins at address 0.
T he ADSP-2100 Family Development Software (Revision
5.02 and later) fully supports the BDMA booting feature and
can generate byte memory space compatible boot code.
T he IDLE instruction can also be used to allow the processor
to hold off execution while booting continues through the
BDMA interface. For BDMA accesses while in Host Mode,
the addresses to boot memory must be constructed externally
to the AD73522. T he only memory address bit provided by
the processor is A0.
ID MA Port Booting
T he AD73522 can also boot programs through its Internal
DMA port. If Mode C = 1, Mode B = 0 and Mode A = 1, the
AD73522 boots from the IDMA port. IDMA feature can load
as much on-chip memory as desired. Program execution is
held off until on-chip program memory location 0 is written
to.
Bus Request and Bus Grant (F ull Memory Mode)
T he AD73522 can relinquish control of the data and address
buses to an external device. When the external device requires
access to memory, it asserts the bus request (BR) signal. If
the AD73522 is not performing an external memory access, it
responds to the active BR input in the following processor
cycle by:
three-stating the data and address buses and the
PMS
,
DMS
,
BMS
,
CMS
,
IOMS
,
RD
,
WR
output drivers,
asserting the bus grant (
BG
) signal, and
halting program execution.
If Go Mode is enabled, the AD73522 will not halt program
execution until it encounters an instruction that requires an
external memory access.
If the AD73522 is performing an external memory access
when the external device asserts the
BR
signal, it will not
three-state the memory interfaces or assert the
BG
signal until
F lag I/O Pins
T he AD73522 has eight general purpose programmable
input/output flag pins. T hey are controlled by two memory
mapped registers. T he PFT YPE register determines the direc-
tion, 1 = output and 0 = input. T he PFDAT A register is used
to read and write the values on the pins. Data being read from
a pin configured as an input is synchronized to the AD73522’s
clock. Bits that are programmed as outputs will read the value
being output. T he PF pins default to input during reset.
In addition to the programmable flags, the AD73522 has
five fixed-mode flags, FLAG_IN, FLAG_OUT , FL0, FL1
and FL 2. FL 0-FL 2 are dedicated output flags. FL AG_IN
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