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参数资料
| 型号： | AD73522 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Dual Analog Front End with Flash based DSP Microcomputer(带闪速DSP微计算机的双模拟前端) |
| 中文描述： | 双模拟前端与闪存的DSP微机（带闪速DSP的微计算机的双模拟前端） |
| 文件页数： | 35/46页 |
| 文件大小： | 654K |
| 代理商： | AD73522 |
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AD73522
–35–
REV. PrC 05/99
Prelimnary Technical Data
DATA
WE
TECHNCAL
F L ASH ME MORY D E SC RIPT ION
T he AD73522 features a 64K x 8 CMOS page mode
EEPROM which can be written with a 3.0-volt-only power
supply. Internal erase/program is transparent to the user.
Featuring high performance page write, the AD73522’s flash
memory provides a typical byte-write time of 39 μsec. T he
entire memory, i.e., 64K bytes, can be written page by page in
as little as 2.5 seconds, when using interface features such as
T oggle Bit or Data Polling to indicate the completion of a
write cycle. T o protect against inadvertent write, the
AD73522 has on-chip hardware and software data protection
schemes.
T he AD73522’s flash memory has a guaranteed page-write
endurance of 10
4
or 10
3
cycles. Data retention is rated at
greater than 100 years. T he AD73522 is suited for
applications that require convenient and economical updating
of program, configuration, or data memory.
F lash Memory C onnection
T he flash memory section of the AD73522 is configured on
the byte-wide DMA bus (BDMA) of the DSP section as
shown in Figure 22. Hence if boot operation is required from
the AD73522’s internal flash memory, the boot mode
selection pins Mode A, Mode B and Mode C should be set to
zero (0).
DATA [0-7]
CE
BYTE
MEMORY
-FLASH
64 kbytes
D
15
D
8
D
17
D
16
A
13
A
0
BMS
AD73522
W R
RD
ADDRESS [0-13]
ADDRESS [14-15]
DB
7
DB
0
A
13
A
0
A
15
A
14
OE
DSP
SECTION
Figure 22. Flash Interface to DSP section
D evice Operation
T he AD73522’s page mode EEPROM offers in-circuit
electrical write capability. T he AD73522 does not require
separate erase and program operations. T he internally timed
write cycle executes both erase and program transparently to
the user. T he AD73522 has industry standard optional
Software Data Protection, which is recommended to be
always enabled.
R ead
T he read operation of the AD73522 is controlled by
BMS
and
RD
, both have to be low for the DSP section to obtain
data from the flash section.
BMS
is used for device selection.
When
BMS
is high, the flash memory is deselected and only
standby power is consumed.
RD
is the output control and is
used to gate data from the flash output pins. T he data bus is
in high impedance state when either
BMS
or
RD
is high.
Refer to the read cycle timing diagram (Figure 24) for further
details.
Write
T he write operation consists of three steps. T he first step is
the optional three byte load sequence for Software Data
Protection. T his is an optional first step in the write
operation, but highly recommended to ensure proper data
integrity. Step 2 is the byte-load cycle to a page buffer of the
flash. Step 3 is an internally controlled write cycle for writing
the data loaded in the page buffer into the memory array for
nonvolatile storage. During the byte-load cycle, the addresses
are latched by the falling edge of either
BMS
or
WR
,
whichever occurs last. T he data is latched by the rising edge
of either
BMS
or
WR
, whichever occurs first. T he internal
write cycle is initiated by a timer after the rising edge of
WR
or
BMS
initiated, will continue to completion, typically within 5 ms.
See Figures 25 and 26 for
WR
and
BMS
controlled page
write cycle timing diagrams.
T he write operation has three functional cycles: the optional
Software Data Protection load sequence, the page load cycle
and the internal write cycle. T he Software Data Protection
consists of a specific three byte load sequence that will leave
the AD73522 protected at the end of the page write. T he
page load cycle consists of loading 1 to 128 bytes of data into
the page buffer. T he internal write cycle consists of the
T BLCO timeout and the write timer operation. During the
write operation, the only valid reads are Data Polling and
T oggle Bit. T he page-write operation allows the loading of up
to 128 bytes of data into the page buffer of the AD73522
flash before the initiation of the internal write cycle. During
the internal write cycle, all the data in the page buffer is
written simultaneously into the memory array. Hence, the
Control Logic
A
15
- A
0
CE (BMS)
OE (RD)
WE (WR)
DB7 - DB0
524288 Bit
EEPROM
Cell Array
Y- Decoder and Page Latches
I/O Buffers and Data Latches
Address Buffer & Latches
X- Decoder
Figure 23. Flash Memory Organisation
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