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参数资料
| 型号： | AD73522 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Dual Analog Front End with Flash based DSP Microcomputer(带闪速DSP微计算机的双模拟前端) |
| 中文描述： | 双模拟前端与闪存的DSP微机（带闪速DSP的微计算机的双模拟前端） |
| 文件页数： | 36/46页 |
| 文件大小： | 654K |
| 代理商： | AD73522 |
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AD73522
–36–
REV. PrC 05/99
Prelimnary Technical Data
DATA
T he AD73522 provides two software means to detect the
completion of a write cycle, in order to optimize the system
write cycle time. T he software detection includes two status
bits: Data Polling (DQ7) and T oggle Bit (DQ6). T he end of
write detection mode is enabled after the rising WE or CE
whichever occurs first, which initiates the internal write cycle.
T he actual completion of the nonvolatile write is
asynchronous with the system; therefore, either a Data Polling
or T oggle Bit read may be simultaneous with the completion
of the write cycle. If this occurs, the system may possibly get
an erroneous result, i.e., valid data may appear to conflict
with either DQ7 or DQ6. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the write cycle, otherwise the rejection
is valid.
Data Polling (DQ7)
When the AD73522 is in the internal write cycle, any attempt
to read DQ7 of the last byte loaded during the byte-load cycle
will receive the complement of the true data. Once the write
cycle is completed, DQ7 will show true data. T he device is
then ready for the next operation. See Figure 27 for Data
Polling timing diagram.
TECHNCAL
byte sequence. See Figures 25 and 26 for the timing
diagrams. T o set the device into the unprotected mode, a six-
byte sequence is required. See Figure 29 for the timing
diagram. If a write is attempted while SDP is enabled the
device will be in a non-accessible state for ~ 300 μs. It is
recommended that Software Data Protection always be
enabled.
T he AD73522 Software Data Protection is a global
command, protecting (or unprotecting) all pages in the entire
memory array once enabled (or disabled). T herefore using
SDP for a single page write will enable SDP for the entire
array. Single pages by themselves cannot be SDP enabled or
disabled. Single power supply reprogrammable nonvolatile
memories may be unintentionally altered. SST strongly
recommends that Software Data Protection (SDP) always be
enabled. T he AD73522 should be programmed using the
SDP command sequence. It is recommended that the SDP
Disable Command Sequence not be issued to the device prior
to writing.
page-write feature of AD73522 allows the entire memory to
be written in as little as 2.5 seconds. During the internal write
cycle, the host is free to perform additional tasks, such as to
fetch data from other locations in the system to set up the
write to the next page. In each page-write operation, all the
bytes that are loaded into the page buffer must have the same
page address, i.e., A7 through A15. Any byte not loaded with
user data will be written to FF. See Figures 25 and 26 for the
page-write cycle timing diagrams. If after the initial byte-load
cycle, the host loads a second byte into the page buffer within
a byte-load cycle time (T BLC) of 100 μs, the AD73522 will
stay in the page load cycle. Additional bytes are then loaded
consecutively. T he page load cycle will be terminated if no
additional byte is loaded into the page buffer within 200 μs
(T BLCO) from the last byte-load cycle, i.e., no subsequent
WR
or
BMS
high-to-low transition after the last rising edge of
WR
or
BMS
. Data in the page buffer can be changed by a
subsequent byte-load cycle. T he page load period can
continue indefinitely, as long as the host continues to load the
device within the byte-load cycle time of 100 μs. T he page to
be loaded is determined by the page address of the last byte
loaded.
Software C hip-E rase
T he AD73522 provides a flash-erase operation, which allows
the user to simultaneously clear the entire flash-memory array
to the “1” state. T his is useful when the entire flash memory
must be quickly erased. T he Software Flash-Erase operation
is initiated by using a specific six byte-load sequence. After
the load sequence, the device enters into an internally timed
cycle similar to the write cycle. During the erase operation,
the only valid read is T oggle Bit. See Figure 30 for timing
diagram.
Write Operation Status Detection
T oggle Bit (DQ6)
During the internal write cycle, any consecutive attempts to
read DQ6 will produce alternating 0’s and 1’s, i.e., toggling
between 0 and 1. When the write cycle is completed, the
toggling will stop. T he device is then ready for the next
operation. See Figure 28 for T oggle Bit timing diagram. T he
initial read of the T oggle Bit will be a “1”.
Data Protection
The AD73522 provides both hardware and software features
to protect nonvolatile data frominadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A
WR
or
BMS
pulse of less than 5
ns will not initiate a write cycle. VDD Power Up/Down
Detection: T he write operation is inhibited when VDD is less
than 2.5V.
Write Inhibit Mode: Forcing
RD
low,
BMS
high, or
WR
high
will inhibit the write operation. T his prevents inadvertent
writes during power-up or power-down.
Software Data Protection (SDP)
T he AD73522 flash-memory provides the JEDEC approved
optional software data protection scheme for all data
alteration operations, i.e., write and chip erase. With this
scheme, any write operation requires the inclusion of a series
of three byte-load operations to precede the data loading
operation. T he three byte-load sequence is used to initiate the
write cycle, providing optimal protection from inadvertent
down. T he AD73522 is shipped with the software data
protection disabled. T he software protection scheme can be
enabled by applying a three-byte sequence to the device,
during a page-load cycle (Figures 25 and 26). T he device will
then be automatically set into the data protect mode. Any
subsequent write operation will require the preceding three-
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