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参数资料
| 型号： | AD73522 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Dual Analog Front End with Flash based DSP Microcomputer(带闪速DSP微计算机的双模拟前端) |
| 中文描述： | 双模拟前端与闪存的DSP微机（带闪速DSP的微计算机的双模拟前端） |
| 文件页数： | 2/46页 |
| 文件大小： | 654K |
| 代理商： | AD73522 |
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AD73522
–2–
REV. PrC 05/99
Prelimnary Technical Data
PRELMNARY
DATA
Figure 1 is an overall block diagram of the AD73522. T he
processor section contains three independent computational
units: the ALU, the multiplier/accumulator (MAC) and the
shifter. T he computational units process 16-bit data directly
and have provisions to support multiprecision computations.
T he ALU performs a standard set of arithmetic and logic
operations; division primitives are also supported. T he MAC
performs single-cycle multiply, multiply/add and multiply/
subtract operations with
40 bits of accumulation. T he shifter performs logical and
arithmetic shifts, normalization, denormalization and derive
exponent operations.
T he internal result (R) bus connects the computational units
so that the output of any unit may be the input of any unit on
the next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. T he sequencer supports conditional jumps, sub-
routine calls and returns in a single cycle. With internal loop
counters and loop stacks, the AD73522 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain loops.
T wo data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one
TECHNCAL
n
processor cycle, where
n
is a scaling value stored in an 8-bit
register (T SCALE). When the value of the count register
reaches zero, an interrupt is generated and the count register
is reloaded from a 16-bit period register (T PERIOD).
AR C HIT E C T UR E OVE R VIE W
T he AD73522 instruction set provides flexible data moves
and multifunction (one or two data moves with a
computation) instructions. Every instruction can be executed
in a single processor cycle. T he AD73522 assembly language
uses an algebraic syntax for ease of coding and readability. A
comprehensive set of development tools supports program
development.
SERIAL PORTS
SPORT 1
SPORT 0
BYTE DMA
CONTROLLER
EXTERNAL
DATA
BUS
ADDRESS
BUS
FULL MEMORY
MODE
MEMORY
PROGRAMMABLE
I/O
AND
FLAGS
16K PM
(OPTIONAL 8K)
TIMER
ADSP-2100 BASE
ARCHITECTURE
SHIFTER
MAC
ALU
ARITHMETIC UNITS
POWER-DOWN
CONTROL
PROGRAM
SEQUENCER
DAG 2
DAG 1
DATA ADDRESS
GENERATORS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
16K DM
(OPTIONAL 8K)
SERIAL PORT
REF
ADC1
ADC2
DAC1
DAC2
ANALOG FRONT END
SECTION
SPORT 2
FLASH
Byte Memory
64 kbytes
Figure 1. Functional Block Diagram
of four possible modify registers. A length value may be
associated with each pointer to implement automatic modulo
addressing for
circular buffers.
T he two address buses (PMA and DMA) share a single
external address bus, allowing memory to be expanded off-
chip, and the two data buses (PMD and DMD) share a single
external data bus. Byte memory space and I/O memory space
also share the external buses.
An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). T he BDMA port is
bidirectional and can directly address up to four megabytes of
external RAM or ROM for off-chip storage of program
overlays or data tables.
T he AD73522 can respond to eleven interrupts. T here can be
up to six external interrupts (one edge-sensitive, two level-
sensitive and three configurable) and seven internal interrupts
generated by the timer, the serial ports (SPORT s), the Byte
DMA port and the power-down circuitry. T here is also a
master RESET signal. T he two serial ports provide a complete
synchronous serial interface with optional companding in
hardware and a wide variety of framed or frameless data transmit
and receive modes of operation.
Each port can generate an internal programmable serial clock
T he AD73522 provides up to 13 general-purpose flag pins.
T he data input and output pins on SPORT 1 can be
alternatively configured as an input flag and an output flag. In
addition, there are eight flags that are programmable as inputs
or outputs and three flags that are always outputs.
A programmable interval timer generates periodic interrupts.
Analog F ront E nd
T he AFE section is configured as a separate block which is
normally connected to either SPORT 0 or SPORT 1 of the
DSP section. As it is not hard-wired to either SPORT the
user has total flexibility in how they wish to allocate system
resources to support the AFE. It is also possible to further
expand the number of analog I/O channels connected to the
SPORT by cascading other single or dual channel AFEs
(AD73311 or AD73322) external to the AD73522.
T he AFE is configured as a cascade of two I/O channels
(similar to that of the discrete AD73322 - refer to the
AD73322 datasheet for more details) with each channel
having a separate 16-bit sigma-delta based ADC and DAC.
Both channels share a common reference whose nominal
value is 1.2V. Figure 2 shows a block diagram of the AFE
section of the AD73522. It shows two channels of ADC and
DAC conversion alog with a common reference.
Communication to both channels is handled by the SPORT 2
block which interfaces to either SPORT 0 or SPORT 1 of the
DSP section.
Figure 3 shows the analog connectivity available on each
channel of the AFE (Channel 1 is detailed here). Both
channels feature fully differential inputs and outputs. T he
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