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参数资料
| 型号： | ADUC834BSZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/80页 |
| 文件大小： | 0K |
| 描述： | IC ADC DUAL16/24BIT W/MCU 52MQFP |
| 产品培训模块： | Process Control |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心处理器： | 8052 |
| 芯体尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 连通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外围设备： | POR，PSM，PWM，温度传感器，WDT |
| 输入/输出数： | 34 |
| 程序存储器容量： | 62KB（62K x 8） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.25 V |
| 数据转换器： | A/D 3x16b，4x24b; D/A 1x12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 52-QFP |
| 包装： | 托盘 |
| 产品目录页面： | 738 (CN2011-ZH PDF) |
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REV. A
–20–
ADuC834
ADC0H/ADC0M/ADC0L (Primary ADC Conversion Result Registers)
These three 8-bit registers hold the 24-bit conversion result from the primary ADC.
SFR Address
ADC0H
High Data Byte
DBH
ADC0M
Middle Data Byte
DAH
ADC0L
Low Data Byte
D9H
Power-On Default Value
00H
ADC0H, ADC0M, ADC0L
Bit Addressable
No
ADC0H, ADC0M, ADC0L
ADC1H/ADC1L (Auxiliary ADC Conversion Result Registers)
These two 8-bit registers hold the 16-bit conversion result from the auxiliary ADC.
SFR Address
ADC1H
High Data Byte
DDH
ADC1L
Low Data Byte
DCH
Power-On Default Value
00H
ADC1H, ADC1L
Bit Addressable
No
ADC1H, ADC1L
OF0H/OF0M/OF0L (Primary ADC Offset Calibration Registers
*)
These three 8-bit registers hold the 24-bit offset calibration coefficient for the primary ADC. These registers are configured at power-on
with a factory default value of 800000H. However, these bytes will be automatically overwritten if an internal or system zero-scale
calibration of the primary ADC is initiated by the user via MD2–0 bits in the ADCMODE Register.
SFR Address
OF0H
Primary ADC Offset Coefficient High Byte
E3H
OF0M
Primary ADC Offset Coefficient Middle Byte
E2H
OF0L
Primary ADC Offset Coefficient Low Byte
E1H
Power-On Default Value
800000H
OF0H, OF0M, OF0L, respectively
Bit Addressable
No
OF0H, OF0M, OF0L
OF1H/OF1L (Auxiliary ADC Offset Calibration Registers
*)
These two 8-bit registers hold the 16-bit offset calibration coefficient for the auxiliary ADC. These registers are configured at power-on
with a factory default value of 8000H. However, these bytes will be automatically overwritten if an internal or system zero-scale cali-
bration of the auxiliary ADC is initiated by the user via the MD2–0 bits in the ADCMODE Register.
SFR Address
OF1H
Auxiliary ADC Offset Coefficient High Byte
E5H
OF1L
Auxiliary ADC Offset Coefficient Low Byte
E4H
Power-On Default Value
8000H
OF1H and OF1L, respectively
Bit Addressable
No
OF1H, OF1L
GN0H/GN0M/GN0L (Primary ADC Gain Calibration Registers
*)
These three 8-bit registers hold the 24-bit gain calibration coefficient for the primary ADC. These registers are configured at power-on
with a factory-calculated internal full-scale calibration coefficient. Every device will have an individual coefficient. However, these
bytes will be automatically overwritten if an internal or system full-scale calibration of the primary ADC is initiated by the user via
MD2–0 bits in the ADCMODE Register.
SFR Address
GN0H
Primary ADC Gain Coefficient High Byte
EBH
GN0M
Primary ADC Gain Coefficient Middle Byte
EAH
GN0L
Primary ADC Gain Coefficient Low Byte
E9H
Power-On Default Value
Configured at Factory Final Test; see Notes above.
Bit Addressable
No
GN0H, GN0M, GN0L
GN1H/GN1L (Auxiliary ADC Gain Calibration Registers
*)
These two 8-bit registers hold the 16-bit gain calibration coefficient for the auxiliary ADC. These registers are configured at power-on
with a factory-calculated internal full-scale calibration coefficient. Every device will have an individual coefficient. However, these
bytes will be automatically overwritten if an internal or system full-scale calibration of the auxiliary ADC is initiated by the user via
MD2–0 bits in the ADCMODE Register.
SFR Address
GN1H
Auxiliary ADC Gain Coefficient High Byte
EDH
GN1L
Auxiliary ADC Gain Coefficient Low Byte
ECH
Power-On Default Value
Configured at Factory Final Test; see Notes above.
Bit Addressable
No
GN1H, GN1L
*These registers can be overwritten by user software only if Mode bits MD0–2 (ADCMODE SFR) are zero.
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