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| 型号： | ADUC834BSZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 35/80页 |
| 文件大小： | 0K |
| 描述： | IC ADC DUAL16/24BIT W/MCU 52MQFP |
| 产品培训模块： | Process Control |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心处理器： | 8052 |
| 芯体尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 连通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外围设备： | POR，PSM，PWM，温度传感器，WDT |
| 输入/输出数： | 34 |
| 程序存储器容量： | 62KB（62K x 8） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.25 V |
| 数据转换器： | A/D 3x16b，4x24b; D/A 1x12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 52-QFP |
| 包装： | 托盘 |
| 产品目录页面： | 738 (CN2011-ZH PDF) |
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REV. A
–40–
ADuC834
TIME INTERVAL COUNTER (WAKE-UP/RTC TIMER)
A time interval counter (TIC) is provided on-chip for:
periodically waking the part up from power-down
implementing a Real-Time Clock
counting longer intervals than the standard 8051 compatible
timers are capable of
The TIC is capable of timeout intervals ranging from 1/128th
second to 255 hours. Furthermore, this counter is clocked by the
crystal oscillator rather than the PLL and thus has the ability to
remain active in power-down mode and time long power-down
intervals. This has obvious applications for remote battery-powered
sensors where regular widely spaced readings are required.
The TIC counter can easily be used to generate a real-time
clock. The hardware will count in seconds, minutes, and hours;
however, user software will have to count in days, months, and
years. The current time can be written to the timebase SFRs
(HTHSEC, SEC, MIN, and HOUR) while TCEN is low. When
the RTC timer is enabled (TCEN is set), the TCEN bit itself
and the HTHSEC, SEC, MIN, and HOUR Registers are not
reset to 00H after a hardware or watchdog timer reset. This is to
prevent the need to recalibrate the real-time clock after a reset.
However, these registers will be reset to 00H after a power cycle
(independent of TCEN) or after any reset if TCEN is clear.
Six SFRs are associated with the time interval counter, TIMECON
being its control register. Depending on the configuration of the
IT0 and IT1 bits in TIMECON, the selected time counter register
overflow will clock the interval counter. When this counter is
equal to the time interval value loaded in the INTVAL SFR, the
TII bit (TIMECON.2) is set and generates an interrupt if enabled.
(See IEIP2 SFR description under Interrupt System in this data
sheet.) If the ADuC834 is in power-down mode, again with TIC
interrupt enabled, the TII bit will wake up the device and resume
code execution by vectoring directly to the TIC interrupt service
vector address at 0053H. The TIC-related SFRs are described
below with a block diagram of the TIC shown in Figure 33.
8-BIT
PRESCALER
HUNDREDTHS COUNTER
HTHSEC
SECOND COUNTER
SEC
MINUTE COUNTER
MIN
HOUR COUNTER
HOUR
TIEN
INTERVAL TIMEOUT
TIME INTERVAL COUNTER INTERRUPT
8-BIT
INTERVAL COUNTER
INTVAL SFR
INTERVAL
TIMEBASE
SELECTION
MUX
TCEN
32.768kHz EXTERNAL CRYSTAL
ITS0, 1
EQUAL?
Figure 33. TIC, Simplified Block Diagram
Table XVIII. TIMECON SFR Bit Designations
Bit
Name
Description
7
–––
Reserved for Future Use
6
–––
Reserved for Future Use. For future product code compatibility, this bit should be written as a ‘1.’
5
ITS1
Interval Timebase Selection Bits
4
ITS0
Written by user to determine the interval counter update rate.
ITS1
ITS0
Interval Timebase
00
1/128 Second
01
Seconds
10
Minutes
11
Hours
3
STI
Single Time Interval Bit.
Set by user to generate a single interval timeout. If set, a timeout will clear the TIEN bit.
Cleared by user to allow the interval counter to be automatically reloaded and start counting again at
each interval timeout.
2
TII
TIC Interrupt Bit.
Set when the 8-bit Interval Counter matches the value in the INTVAL SFR.
Cleared by user software.
1
TIEN
Time Interval Enable Bit.
Set by user to enable the 8-bit time interval counter.
Cleared by user to disable and clear the contents of the 8-bit interval counter. To ensure that the
8-bit interval counter is cleared TIEN must be held low for at least 30.5 s (32 kHz).
0
TCEN
Time Clock Enable Bit.
Set by user to enable the time clock to the time interval counters.
Cleared by user to disable the 32 kHz clock to the TIC and clear the 8-bit prescaler and the HTHSEC,
SEC, MIN and HOURS SFRs. To ensure that these registers are cleared, TCEN must be held low for at
least 30.5 s (32 kHz). The time registers (HTHSEC, SEC, MIN, and HOUR) can only be written
while TCEN is low.
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