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参数资料
| 型号： | ADUC834BSZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 47/80页 |
| 文件大小： | 0K |
| 描述： | IC ADC DUAL16/24BIT W/MCU 52MQFP |
| 产品培训模块： | Process Control |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心处理器： | 8052 |
| 芯体尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 连通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外围设备： | POR，PSM，PWM，温度传感器，WDT |
| 输入/输出数： | 34 |
| 程序存储器容量： | 62KB（62K x 8） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.25 V |
| 数据转换器： | A/D 3x16b，4x24b; D/A 1x12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 52-QFP |
| 包装： | 托盘 |
| 产品目录页面： | 738 (CN2011-ZH PDF) |
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REV. A
ADuC834
–51–
Notice also that direct access to the SCLOCK and SDATA/MOSI
pins is afforded through the SFR interface in I
2C master mode.
Therefore, if you are not using the SPI or I
2C functions, you can
use these two pins to give additional high current digital outputs.
HARDWARE SPI
(MASTER/SLAVE)
Q3
SCHMITT
TRIGGER
Q1
Q2 (OFF)
DVDD
SCLOCK
PIN
Q4 (OFF)
SPE = 1 (SPI ENABLE)
Figure 42. SCLOCK Pin I/O Functional Equivalent in
SPI Mode
MCO
I2CM
SFR
BITS
50ns GLITCH
REJECTION FILTER
HARDWARE I2C
(SLAVE ONLY)
Q3
Q4
SCLOCK
PIN
Q2
Q1
(OFF)
DVDD
SPE = 0 (I2C ENABLE)
Figure 43. SCLOCK Pin I/O Functional Equivalent in
I2C Mode
HARDWARE SPI
(MASTER/SLAVE)
Q3
Q1
Q2 (OFF)
DVDD
SDATA/
MOSI
PIN
Q4 (OFF)
SPE = 1 (SPI ENABLE)
Figure 44. SDATA/MOSI Pin I/O Functional Equivalent
in SPI Mode
Q3
Q4
Q2
Q1
(OFF)
DVDD
MDI
MDO
MDE
I2CM
HARDWARE I2C
(SLAVE ONLY)
50ns GLITCH
REJECTION FILTER
SDATA/
MOSI
PIN
SFR
BITS
SPE = 0 (I2C ENABLE)
Figure 45. SDATA/MOSI Pin I/O Functional Equivalent
in I2C Mode
As shown in Figure 46, the MISO pin in SPI master/slave
operation offers the exact same pull-up and pull-down configu-
ration as the MOSI pin in SPI slave/master operation.
The
SS pin has a weak internal pull-up permanently enabled to
prevent the
SS input from floating. This pull-up can be easily
overdriven by an external device to drive the
SS pin low.
HARDWARE SPI
(MASTER/SLAVE)
MISO
PIN
DVDD
Figure 46. MISO Pin I/O Functional Equivalent
HARDWARE SPI
(MASTER/SLAVE)
SS
PIN
DVDD
Figure 47.
SS Pin I/O Functional Equivalent
Read-Modify-Write Instructions
Some 8051 instructions that read a port read the latch and
others read the pin. The instructions that read the latch rather
than the pins are the ones that read a value, possibly change it,
and then rewrite it to the latch. These are called “read-modify-
write” instructions. Listed below are the read-modify-write
instructions. When the destination operand is a port, or a port
bit, these instructions read the latch rather than the pin.
ANL
(Logical AND, e.g., ANL P1, A)
ORL
(Logical OR, e.g., ORL P2, A)
XRL
(Logical EX-OR, e.g., XRL P3, A)
JBC
(Jump If Bit = 1 and Clear Bit,
e.g., JBC P1.1, LABEL
CPL
(Complement Bit, e.g., CPL P3.0)
INC
(Increment, e.g., INC P2)
DEC
(Decrement, e.g., DEC P2)
DJNZ
(Decrement and Jump IFf Not Zero,
e.g.,DJNZ P3, LABEL)
MOV PX.Y, C* (Move Carry to Bit Y of Port X)
CLR PX.Y*
(Clear Bit Y of Port X)
SETB PX.Y*
(Set Bit Y of Port X)
The reason that read-modify-write instructions are directed to
the latch rather than the pin is to avoid a possible misinterpreta-
tion of the voltage level of a pin. For example, a port pin might
be used to drive the base of a transistor. When a 1 is written to
the bit, the transistor is turned on. If the CPU then reads the
same port bit at the pin rather then the latch, it will read the
base voltage of the transistor and interpret it as a Logic 0. Read-
ing the latch rather than the pin will return the correct value of 1.
*These instruction read the port byte (all 8 bits), modify the addressed bit and
then write the new byte back to the latch.
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