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参数资料
| 型号： | ADUC834BSZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 26/80页 |
| 文件大小： | 0K |
| 描述： | IC ADC DUAL16/24BIT W/MCU 52MQFP |
| 产品培训模块： | Process Control |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心处理器： | 8052 |
| 芯体尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 连通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外围设备： | POR，PSM，PWM，温度传感器，WDT |
| 输入/输出数： | 34 |
| 程序存储器容量： | 62KB（62K x 8） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.25 V |
| 数据转换器： | A/D 3x16b，4x24b; D/A 1x12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 52-QFP |
| 包装： | 托盘 |
| 产品目录页面： | 738 (CN2011-ZH PDF) |
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REV. A
–32–
ADuC834
BYTE 1
(0000H)
EDATA1
SFR
BYTE 1
(0004H)
BYTE 1
(0008H)
BYTE 1
(000CH)
BYTE 1
(0FF8H)
BYTE 1
(0FFCH)
BYTE 2
(0001H)
EDATA2
SFR
BYTE 2
(0005H)
BYTE 2
(0009H)
BYTE 2
(000DH)
BYTE 2
(0FF9H)
BYTE 2
(0FFDH)
BYTE 3
(0002H)
EDATA3
SFR
BYTE 3
(0006H)
BYTE 3
(000AH)
BYTE 3
(000EH)
BYTE 3
(0FFAH)
BYTE 3
(0FFEH)
BYTE 4
(0003H)
EDATA4
SFR
BYTE 4
(0007H)
BYTE 4
(000BH)
BYTE 4
(000FH)
BYTE 4
(0FFBH)
BYTE 4
(0FFFH)
01H
00H
02H
03H
3FEH
3FFH
PAGE
ADDRESS
(E
A
D
RH/L)
BYTE
ADDRESSES
ARE GIVEN IN
BRACKETS
Using the Flash/EE Data Memory
The 4 Kbytes of Flash/EE data memory is configured as 1024 pages,
each of 4 bytes. As with the other ADuC834 peripherals, the
interface to this memory space is via a group of registers mapped
in the SFR space. A group of four data registers (EDATA1–4)
is used to hold the 4 bytes of data at each page. The page is
addressed via the two registers EADRH and EADRL. Finally,
ECON is an 8-bit control register that may be written with one
of nine Flash/EE memory access commands to trigger various
read, write, erase, and verify functions.
A block diagram of the SFR interface to the Flash/EE data
memory array is shown in Figure 20.
ECON—Flash/EE Memory Control SFR
Programming of either the Flash/EE data memory or the Flash/EE
program memory is done through the Flash/EE Memory Control
SFR (ECON). This SFR allows the user to read, write, erase or
verify the 4 Kbytes of Flash/EE data memory or the 56 Kbytes
of Flash/EE program memory.
Table XIV.
ECON—Flash/EE Memory Commands
Command Description
ECON Value
(Normal Mode) (Power-On Default)
(ULOAD Mode)
01H
Results in 4 bytes in the Flash/EE data memory,
Not Implemented. Use the MOVC instruction.
READ
addressed by the page address EADRH/L,
being read into EDATA 1 to 4.
02H
Results in 4 bytes in EDATA1–4 being written to the
Results in bytes 0–255 of internal XRAM being written
WRITE
Flash/EE data memory, at the page address given by
to the 256 bytes of Flash/EE program memory at the page
EADRH. (0
≤ EADRH < 0400H)
address given by EADRH/L (0
≤ EADRH/L < E0H)
Note: The 4 bytes in the page being addressed must
Note: The 256 bytes in the page being addressed must
be pre-erased.
03H
Reserved Command
04H
Verifies if the data in EDATA1–4 is contained in the
Not Implemented. Use the MOVC and MOVX instructions
VERIFY
page address given by EADRH/L. A subsequent read
to verify the WRITE in software.
of the ECON SFR will result in a 0 being read if the
verification is valid, or a nonzero value being read to
indicate an invalid verification.
05H
Results in the erase of the 4 bytes page of Flash/EE data
Results in the 64-bytes page of Flash/EE program memory,
ERASE PAGE
memory addressed by the page address EADRH/L
addressed by the byte address EADRH/L being erased.
EADRL can equal any of 64 locations within the page. A new
page starts whenever EADRL is equal to 00H, 40H, 80H, or C0H
06H
Results in the erase of entire 4 Kbytes of Flash/EE
Results in the erase of the entire 56 Kbytes of ULOAD
ERASE ALL
data memory.
Flash/EE program memory
81H
Results in the byte in the Flash/EE data memory,
Not Implemented. Use the MOVC command.
READBYTE
addressed by the byte address EADRH/L, being read
into EDATA1. (0
≤ EADRH/L ≤ 0FFFH).
82H
Results in the byte in EDATA1 being written into
WRITEBYTE
Flash/EE data memory, at the byte address EADRH/L. Flash/EE program memory at the byte address
EADRH/L (0
≤ EADRH/L ≤ DFFFH)
0FH
Leaves the ECON instructions to operate on the
Enters normal mode directing subsequent ECON
EXULOAD
Flash/EE data memory.
instructions to operate on the Flash/EE data memory
F0H
Enters ULOAD mode, directing subsequent ECON
Leaves the ECON Instructions to operate on the Flash/EE
ULOAD
instructions to operate on the Flash/EE program memory. program memory.
Figure 20. Flash/EE Data Memory Control and Configuration
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