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| 型号： | ADUC834BSZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 78/80页 |
| 文件大小： | 0K |
| 描述： | IC ADC DUAL16/24BIT W/MCU 52MQFP |
| 产品培训模块： | Process Control |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心处理器： | 8052 |
| 芯体尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 连通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外围设备： | POR，PSM，PWM，温度传感器，WDT |
| 输入/输出数： | 34 |
| 程序存储器容量： | 62KB（62K x 8） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.25 V |
| 数据转换器： | A/D 3x16b，4x24b; D/A 1x12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 52-QFP |
| 包装： | 托盘 |
| 产品目录页面： | 738 (CN2011-ZH PDF) |
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REV. A
–8–
ADuC834
NOTES
1 Temperature Range for ADuC834BS (MQFP package) is –40°C to +125°C.
Temperature Range for ADuC834BCP (CSP package) is –40
°C to +85°C.
2 These numbers are not production tested but are guaranteed by design and/or characterization data on production release.
3 System Zero-Scale Calibration can remove this error.
4 The primary ADC is factory calibrated at 25°C with AVDD = DVDD = 5 V yielding this full-scale error of 10 V. If user power supply or temperature conditions are
significantly different from these, an Internal Full-Scale Calibration will restore this error to 10
V. A system zero-scale and full-scale calibration will remove this
error altogether.
5 Gain Error Drift is a span drift. To calculate Full-Scale Error Drift, add the Offset Error Drift to the Gain Error Drift times the full-scale input.
6 The auxiliary ADC is factory calibrated at 25°C with AVDD = DVDD = 5 V yielding this full-scale error of –2.5 LSB. A system zero-scale and full-scale calibration
will remove this error altogether.
7 DAC linearity and ac specifications are calculated using: reduced code range of 48 to 4095, 0 to V
REF; reduced code range of 100 to 3950, 0 to V DD.
8 Gain Error is a measure of the span error of the DAC.
9 In general terms, the bipolar input voltage range to the primary ADC is given by RangeADC = ± (VREF 2RN)/125, where:
VREF = REFIN(+) to REFIN(–) voltage and VREF = 1.25 V when internal ADC VREF is selected. RN = decimal equivalent of RN2, RN1, RN0, e.g., VREF = 2.5 V
and RN2, RN1, RN0 = 1, 1, 0 the RangeADC =
± 1.28 V. In unipolar mode, the effective range is 0 V to 1.28 V in our example.
10 1.25 V is used as the reference voltage to the ADC when internal V
REF is selected via XREF0 and XREF1 bits in ADC0CON and ADC1CON, respectively.
11 In bipolar mode, the Auxiliary ADC can only be driven to a minimum of AGND – 30 mV as indicated by the Auxiliary ADC absolute AIN voltage limits. The
bipolar range is still –VREF to +VREF; however, the negative voltage is limited to –30 mV.
12 The ADuC834BCP (CSP Package) has been qualified and tested with the base of the CSP Package floating.
13 Pins configured in SPI Mode, pins configured as digital inputs during this test.
14 Pins configured in I2C Mode only.
15 Flash/EE Memory Reliability Characteristics apply to both the Flash/EE program memory and Flash/EE data memory.
16 Endurance is qualified to 100 Kcycles as per JEDEC Std. 22 method A117 and measured at –40 °C, +25°C, +85°C, and +125°C. Typical endurance at 25°C
is 700 Kcycles.
17 Retention lifetime equivalent at junction temperature (T
J) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV
will derate with junction temperature as shown in Figure 16 in the Flash/EE Memory section of this data sheet.
18 Power Supply current consumption is measured in Normal, Idle, and Power-Down modes under the following conditions:
Normal mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, Core Executing internal software loop.
Idle mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, PCON.0 = 1, Core Execution suspended in idle mode.
Power-Down mode: Reset = 0.4 V, All P0 pins and P1.2–P1.7 Pins = 0.4 V, All other digital I/O pins are open circuit, Core Clk changed via CD bits in
PLLCON, PCON.1 = 1, Core Execution suspended in power-down mode, OSC turned ON or OFF via OSC_PD bit (PLLCON.7) in PLLCON SFR.
19 DV
DD power supply current will increase typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle.
Specifications subject to change without notice.
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