参数资料
型号: B900J24PXX12I
元件分类: 数字信号处理
英文描述: 0-BIT, 80 MHz, OTHER DSP, PQFP44
文件页数: 19/100页
文件大小: 1547K
代理商: B900J24PXX12I
Lucent Technologies Inc.
25
Advance Data Sheet
B900
July 1999
Baseband Signal Processor
4 Hardware Architecture (continued)
4.4
Memory Maps and Wait-States (continued)
4.4.1 Instruction/Coefficient Memory Map Selection (continued)
Whenever the device is reset using the RSTB pin, the default memory map is MAP1. A reset through the JTAG port
does not reinitialize the alf register, so the previous memory map is retained.
4.4.2 Data Memory Map Selection
Table 13 shows the data memory maps.
Table 12. Instruction/Coefficient Memory Map (X Memory Space)
Decimal
Address
Hexadecimal
Address in
PC, pt, pi, pr
MAP1
(LOWPR = 0)*
* LOWPR is an alf register bit. The Lucent development system tools can independently
set the memory map.
MAP3
(LOWPR = 1)
MAP3 is not available if the mask-programmable secure option is selected.
0
2047
0x0000
0x07FF
ROM
RAM1, 2
2048
8191
0x0800
0x1FFF
Reserved
8192
16,383
0x2000
0x3FFF
16,384
24,575
0x4000
0x5FFF
ROM
24,576
32,767
0x6000
0x7FFF
Reserved
32,768
40,959
0x8000
0x9FFF
40,960
49,151
0xA000
0xBFFF
Reserved
49,152
51,199
0xC000
0xC7FF
RAM1, 2
51,200
57,343
0xC800
0xDFFF
Reserved
57,344
65,535
0xE000
0xFFFF
Table 13. Data (Y) Memory Map
Decimal
Address
Address in r0,
r1, r2, r3
Segment
0
2047
0x0000
0x07FF
RAM1, 2
2048
65,535
0x0800
0xFFFF
Reserved
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