- 您现在的位置：买卖IC网 > PDF目录166397 > B900J24PXX12I 0-BIT, 80 MHz, OTHER DSP, PQFP44 PDF资料下载
参数资料
| 型号： | B900J24PXX12I |
| 元件分类： | 数字信号处理 |
| 英文描述： | 0-BIT, 80 MHz, OTHER DSP, PQFP44 |
| 文件页数： | 41/100页 |
| 文件大小： | 1547K |
| 代理商： | B900J24PXX12I |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页当前第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页
Lucent Technologies Inc.
45
Advance Data Sheet
B900
July 1999
Baseband Signal Processor
5 Software Architecture (continued)
5.1
Instruction Set (continued)
5.1.6 F4 BMU Instructions (continued)
s
Barrel Shifter
s
Normalization and Exponent Computation
aD = aS >> IM16
Arithmetic right shift by immediate (36-bit, sign filled in); 2-cycle,
2-word.
aD = aS >> arM
Arithmetic right shift by arM (36-bit, sign filled in); 1-cycle.
aD = aS >> aS
Arithmetic right shift by aS (36-bit, sign filled in); 2-cycle.
aD = aS >>> IM16 Logical right shift by immediate (32-bit, 0s filled in); 2-cycle, 2-word.
aD = aS >>> arM
Logical right shift by arM (32-bit, 0s filled in); 1-cycle.
aD = aS >>> aS
Logical right shift by aS (32-bit, 0s filled in); 2-cycle.
aD = aS << IM16
Arithmetic left shift* by immediate (36-bit, 0s filled in); 2-cycle, 2-word.
* Not the same as the special function arithmetic left shift. Here, the guard bits in the destination accumulator are shifted into, not sign-
extended.
aD = aS << arM
Arithmetic left shift* by arM (36-bit, 0s filled in); 1-cycle.
aD = aS << aS
Arithmetic left shift* by aS (36-bit, 0s filled in); 2-cycle.
aD = aS <<< IM16 Logical left shift by immediate (36-bit, 0s filled in); 2-cycle, 2-word.
aD = aS <<< arM
Logical left shift by arM (36-bit, 0s filled in); 1-cycle.
aD = aS <<< aS
Logical left shift by aS (36-bit, 0s filled in); 2-cycle.
aD = exp(aS)
Detect the number of redundant sign bits in accumulator; 1-cycle.
aD = norm (aS, arM)
Normalize aS with respect to bit 31, with exponent in arM; 1-cycle.
相关PDF资料 |
PDF描述 |
|---|---|
| B900J24FXX12IT | 0-BIT, 59.88 MHz, OTHER DSP, PQFP44 |
| BA00CC0WCP-V5 | 1A Low Dropout Voltage Regulator with Shut Down Switch(Adustable Voltage) |
| BA10E6 | COPPER ALLOY, TIN FINISH, RING TERMINAL |
| BA12004 | 0.5 A, 7 CHANNEL, NPN, Si, POWER TRANSISTOR |
| BA1518SUR5VP | SINGLE COLOR DISPLAY CLUSTER, ULTRA RED |
相关代理商/技术参数 |
参数描述 |
|---|---|
| B-900-M-10 | 制造商:Thomas & Betts 功能描述: |
| B-900-M-10-EG | 制造商:Thomas & Betts 功能描述: |
| B-900-M-20 | 制造商:Thomas & Betts 功能描述: |
| B-900-M-20-EG | 制造商:Thomas & Betts 功能描述: |
| B901 | 制造商:EDAL 制造商全称:EDAL 功能描述:Silicon Bridge Rectifier |
发布紧急采购，3分钟左右您将得到回复。