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参数资料
| 型号： | B900J24PXX12I |
| 元件分类： | 数字信号处理 |
| 英文描述： | 0-BIT, 80 MHz, OTHER DSP, PQFP44 |
| 文件页数： | 23/100页 |
| 文件大小： | 1547K |
| 代理商： | B900J24PXX12I |
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Lucent Technologies Inc.
29
Advance Data Sheet
B900
July 1999
Baseband Signal Processor
4 Hardware Architecture (continued)
4.6
Synchronous Serial Interface (SSI)
The SSI can be programmed in the master or slave mode. The control word can be written to a 16-bit control regis-
ter, ssic, to configure the SSI. The byte to be transmitted is written into the 8-bit data register, ssid. As a master,
the SSI initiates serial transmission of a byte. This occurs whenever the master writes a byte to the data register
(provided there is no transmission in progress). As a slave, it waits until the master initiates the start of transfer. In
either case, transmitting and receiving occur simultaneously at the master and slave.
The byte from the data register of the master is shifted into the data register of the slave and vice versa. The two
registers operate as a 16-bit circular shift register, wherein the most significant bit (MSB) of the master data register
is simultaneously shifted into the least significant bit (LSB) of the slave data register and the MSB of the slave data
register is shifted into the LSB of the master data register. The B900 reads the received byte as a 16-bit word. The
lower byte is the received data, and it is sign extended into the upper byte. The shift clock is provided by the master.
Depending on the polarity of the shift clock and the phase of the transfer relative to the shift clock, the master oper-
ates in one of four different modes of transfer. These modes are under program control and must match the mode
used by the peripheral device with which the SSI communicates. In addition, there are seven different clock rates
that the master can choose from as the rate at which the bits are to be shifted out. The status of the transfer is indi-
cated by three status bits, included as read-only bits in the control register. These indicate end of transfer and any
errors that may have occurred.
Note: Table 17 on page 30 describes the SSI pins.
5-6147 (F)
Figure 7. SSI Interconnections
INTERRUPT
TO/FROM
CORE
IDB
RD_SSIC
WR_SSIC
RD_SSID
WR_SSID
ID
B
C
O
N
T
ROL
LI
NE
S
SSI
SCK
MDOSDI
MDISDO
SSN
I/
O
BU
F
E
R
S
IOPC5/SCK
IOPC6/MDOSDI
IOPC7/MDISDO
IOPC4/SSN
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相关代理商/技术参数 |
参数描述 |
|---|---|
| B-900-M-10 | 制造商:Thomas & Betts 功能描述: |
| B-900-M-10-EG | 制造商:Thomas & Betts 功能描述: |
| B-900-M-20 | 制造商:Thomas & Betts 功能描述: |
| B-900-M-20-EG | 制造商:Thomas & Betts 功能描述: |
| B901 | 制造商:EDAL 制造商全称:EDAL 功能描述:Silicon Bridge Rectifier |
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