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| 型号： | B900J24PXX12I |
| 元件分类： | 数字信号处理 |
| 英文描述： | 0-BIT, 80 MHz, OTHER DSP, PQFP44 |
| 文件页数： | 46/100页 |
| 文件大小： | 1547K |
| 代理商： | B900J24PXX12I |
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Lucent Technologies Inc.
5
Advance Data Sheet
B900
July 1999
Baseband Signal Processor
Table of Contents (continued)
Table
Page
Table 1. B900 Pinout .............................................................................................................................................. 11
Table 2. B900 Power Supply, Ground, and Unconnected Pins .............................................................................. 11
Table 3. System Interface....................................................................................................................................... 12
Table 4. Synchronous Serial Interface (SSI) .......................................................................................................... 12
Table 5. I/O Port Interface (IOP)............................................................................................................................. 13
Table 6. JTAG Test Mode Interface........................................................................................................................ 14
Table 7. PWR/GND ................................................................................................................................................ 14
Table 8. B900 Block Diagram Legend .................................................................................................................... 17
Table 9. DOUT Pin Output Functions ..................................................................................................................... 19
Table 10. DSP1600 Core Block Diagram Legend .................................................................................................. 21
Table 11. Interrupt Vectors ..................................................................................................................................... 23
Table 12. Instruction/Coefficient Memory Map (X Memory Space) ........................................................................ 25
Table 13. Data (Y) Memory Map ............................................................................................................................ 25
Table 14. Clock Options ......................................................................................................................................... 26
Table 15. Clock Switch Latencies........................................................................................................................... 28
Table 16. Core Clock Stabilization Requirements .................................................................................................. 28
Table 17. SSI Pin Descriptions ............................................................................................................................... 30
Table 18. IOP Operation......................................................................................................................................... 31
Table 19. IOP Pin Multiplexing ............................................................................................................................... 32
Table 20. SIO Read/Write Pointer Operation ......................................................................................................... 36
Table 21. Instruction Set Operators........................................................................................................................ 39
Table 22. F1 Multiply/ALU Instructions ................................................................................................................... 40
Table 23. Replacement Table for F1 Multiply/ALU Instructions.............................................................................. 40
Table 24. F2 Special Function Instructions............................................................................................................. 41
Table 25. Replacement Table for F2 Special Function Instructions ....................................................................... 41
Table 26. Control Instructions................................................................................................................................. 42
Table 27. Replacement Table for Control Instructions ........................................................................................... 42
Table 28. B900 Conditional Mnemonics ................................................................................................................. 43
Table 29. F3 ALU Instructions ................................................................................................................................ 44
Table 30. Replacement Table for F3 ALU Instructions........................................................................................... 44
Table 31. Replacement Table for F4 BMU Instructions.......................................................................................... 46
Table 32. Cache Instructions .................................................................................................................................. 47
Table 33. Replacement Table for Cache Instructions............................................................................................. 47
Table 34. Data Move Instructions ........................................................................................................................... 48
Table 35. Replacement Table for Data Move Instructions...................................................................................... 48
Table 36. alf (Standby and Memory Map) Register................................................................................................ 49
Table 37. auc (Arithmetic Unit Control) Register.................................................................................................... 50
Table 38. cbit<a—d> (IOP Control Bit) and sbit<a—d> (IOP Status Bit) Registers ............................................. 50
Table 39. chipc Register Fields ............................................................................................................................. 51
Table 40. chipo Register Fields ............................................................................................................................. 52
Table 41. clkc Register Fields................................................................................................................................ 53
Table 42. inc (Interrupt Control) Register............................................................................................................... 54
Table 43. ins (Interrupt Status) Register ................................................................................................................ 54
Table 44. IOPUC<a—d> Register Fields................................................................................................................ 55
Table 45. JTAG ID Register (32-bit) ....................................................................................................................... 56
Table 46. JTAG ROMCODE Letter Values............................................................................................................. 56
Table 47. pllc Register Fields................................................................................................................................. 57
Table 48. psw (Processor Status Word) Register .................................................................................................. 57
Table 49. sbit<a—d> (IOP Status Bit) and cbit<a—d> (IOP Control Bit) Registers ............................................. 58
Table 50. SIO Control Register (sioc) Fields ......................................................................................................... 59
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