参数资料
型号: GT-48208
厂商: Galileo Technology Services, LLC
英文描述: Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高级交换式 10+10/100 BaseX以太网控制器)
中文描述: 先进的交换式以太网控制器的10 10/100 BaseX(高级交换式10 10/100 BaseX以太网控制器)
文件页数: 11/135页
文件大小: 1619K
代理商: GT-48208
GT-482xx Switched Ethernet Controllers for 10+10/100 BaseX
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Revision 1.2
MIB counters can be cleared by reading, or left intact after a read based on the MIB Clear Mode (bit 21 in the Glo-
bal Command Register.) During initialization, the CPU must read all of the MIB counters in order to reset the
counters to ‘0’. The counters will only be reset to ‘0’ if MIBClrMode (bit 21 of the Global Control Register) is set to
‘0’ (default). If MIBClrMode bit is ‘1’, reading the MIB counters will have no effect.
Table 62 lists the definitions for terms used in the counter descriptions.
Table 62: Definitions Used in Counter Descriptions
Te r m
D e finition
Packet Data Section
All data bytes in the packet following the SFD until the end of the packet
Packet Data Length
The number of data bytes in the packet data section
Data Octet
A single byte from the packet data section
Nibble
4 bits (half byte) of a data octet
Misaligned Packet
A packet with an odd number of nibbles
Received Good Packet
A received packet which is not rejected and enters the switching core to be transmit-
ted later
Transmitted Good
Packet
Any transmitted packet from the GT-482xx
Collision Event
A collision has been detected until than 576 bit times into the transmitted packet
after TxEn.
Late Collision Event
A collision has been detected later than 576 bit times into the transmitted packet
after TxEn.
Rx Error Event
The input RX_ERR has been asserted
Dropped Packet
A received packet which is ignored due to lack of available receive buffers (port is in
buffer_full state)
Local Packet
A received packet whose destination address is mapped to the receiving port
Rejected Packet
A received packet which is not forwarded due to error such as bad CRC, Rx Error
Event, Invalid size (too short or too long).
MIBCtrMode
Bit 26, MIBCtrMode, of the Global Control Register (offset 0x140028)
VTagEn
Bit 9, VTagEn, of the Port Control Register (offset 0x040200-0x040204)
MAXFRAMESIZE
1518 for VTagEn = 0 (default) or 1536 for VTagEn = 1
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