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参数资料
型号： GT-48208
厂商： Galileo Technology Services, LLC
英文描述： Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高级交换式 10+10/100 BaseX以太网控制器)
中文描述： 先进的交换式以太网控制器的10 10/100 BaseX（高级交换式10 10/100 BaseX以太网控制器）
文件页数： 38/135页
文件大小： 1619K
代理商： GT-48208
GT-482xx Switched Ethernet Controllers for 10+10/100 BaseX
GALI
LEO
TECHNOLOGY
CONFI
D
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AL
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DO
NOT
REPRODUCE
132
Revision 1.2
PRELIMINARY
1.2
1/27/99
1. Applied new template and format.
2. Added List of Tables and Figures.
3. Added a block diagram illustrating a typical managed
switch with two 100Mbit ports + 12 10 Mbit ports.
4. Changed AClk max frequency to 66MHz and CClk
max frequency to 50MHz.
5. CClk frequency must be higher than 25% of AClk and
lower than total AClk.
6. Changed RxClk and TxClk on the expansion port to
max 60MHz frequency .
7. Added Appendix A on page135, illustration of the
IGMP packet formats.
8. Section 1.1 "Fast Ethernet Ports" on page 9, added
information about two Galaxy devices connected with
an expansion port.
9. Section 1.6 "Address Recognition" on page 10,
changed the number of different Unicast MAC
addresses and unlimited Multicast/Broadcast MAC
addresses recognized by GT-482xx from 8000 to
8192, and (2000 changed to 2,024 in 1Mbyte configu-
ration).
10. The following changes were made to Table 2, “Pin
Functions,” on page 14:
- Symbol for DRAM Address changed from Addr[11:0]
to DAddr[11:0]
- In the description for the TxEN[0] symbol: Transmit
Enable, added that packet is transmitted on Port 0
- Corrected description "It should be driven at the fall-
ing edge of the clock" to "It should be driven at the
falling edge of the LEDClk"
- Corrected description for the MDIO symbol: Man-
agement Data Input/Output.
- Corrected description for the LEDClk symbol
- Added polarity information for Link Status and Serial
Link Status Indication
11. Table 4, “GT-482xx DRAM Address Mapping,” on
page 24, changed 1Mbyte address for CPU descrip-
tors.
12. Section 6.1 "Forwarding Mask" on page 26, added
"When the GT-482XX performs new address learning,
the forw[14:0] bits are set to 0x7FFF (all 1's)".
13. Section 1.6 "Address Recognition" on page 10, cor-
rected note about the treatment of incoming PAUSE
packets when flow control is disabled.
14. Section 4. "Microarchitectural Overview" on page 21,
corrected FIFO size in 10Mbit port and 100Mbit port
units.
15. Section 6.3 "Address Learning Process" on page 27,
added information specific to two device configura-
tions.
Table 77: Document History (Continued)
D o cum e nt Ty pe
R e v. #
D at e
C omment s
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