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参数资料
型号： GT-48208
厂商： Galileo Technology Services, LLC
英文描述： Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高级交换式 10+10/100 BaseX以太网控制器)
中文描述： 先进的交换式以太网控制器的10 10/100 BaseX（高级交换式10 10/100 BaseX以太网控制器）
文件页数： 64/135页
文件大小： 1619K
代理商： GT-48208
GT-482xx Switched Ethernet Controllers for 10+10/100 BaseX
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the second word (Valid bit) is automatically cleared when the CPU reads the register. If this bit is not
cleared when the GT-482xx attempts to write, the next descriptor is reloaded when the valid bit is reset.
An interrupt is asserted (if not masked) when a new descriptor is successfully written.
CPU_EL_Free_Req register. This 32-bit register is written by the CPU to signal to the GT-482xx that the
buffer can be cleared in the SDRAM (typically this is done after the CPU has read the packet from the
GT-482xx memory). The GT-482xx clears the busy bit in this register when it is ready to receive another
command. The CPU reads this register before writing to it to check that it is clear.
The sequence for forwarding a Unicast packet to the CPU is as follows:
1.
The incoming packet is fed to the Receive FIFO and transferred to an empty block in the DRAM.
2.
In parallel, an address recognition cycle is performed for the SA and the DA (Unicast or Multicast).
3.
At the end of a good packet transfer, the packet is forwarded to the CPU Tx queue. The packet is for-
warded by writing the following information to the Tx-descriptor pointed to by the queue Producer: type
(packet/NA), source port#, byte count, buffer address. In addition the relevant bits are set: Multicast, Uni-
cast, Broadcast, Intervention, Unknown, New_Address, EASE. In the case of Multicast/Broadcast pack-
ets, the GT-482xx sets the Multicast Indicator bits in the SDRAM.
4.
The CPU Tx High/Low Queue Producer index is incremented. When the Write pointer is not equal to the
Read pointer, the GT-482xx checks if the CPU_Tx_High/Low_Desc register can be loaded, if it can be
loaded, the descriptor pointed by the Read pointer is loaded into the CPU_Tx_High/Low_Desc register
and the Read pointers incremented. The CPU is then interrupted.
5.
The CPU reads the CPU_Tx_High/Low_Desc register. The CPU can read/write to the packet buffer
directly. When completed the CPU writes an End_Of_Packet message to the CPU_EL_Free_Req regis-
ter.
6.
After getting the End_Of_Packet message, the GT-482xx clears the Multicast indicator bit of the CPU (if
it was Multicast) and if cleared - resets the appropriate bit in the empty list and decrements the
rx_block_counter of the source port.
7.
Instead of stages (5) and (6) above, the CPU can enqueue the packet for transmission (without copying
to another buffer, but after modifying it). This mechanism applies only to Unicast packets, or to Multicast-
packets that were forwarded only to the CPU. This may be useful when the CPU wants to do intervention
on traffic and redirect it (after optionally modifying the packet contents), without copying the entire packet
to its memory. The Source port number written to the CPU Enqueue register should be the original
source port number and not the CPU (port number 0xE).
7.4
Forwarding a Packet from the CPU to the GT-482xx
This interface is used to transmit packets from the CPU to the Ethernet ports. The CPU requests the next empty
buffer, writes to the DRAM directly, and then requests queueing of a single packet to a port Tx queue (equivalent
to End_Of_Packet message in the GalNet Architecture Family).
CPU packet transmission is performed with a simple register interface that allows handling one packet enqueue at
a time. Getting empty buffer addresses and enqueueing packets are two independent mechanisms - for example:
the CPU can re-enqueue packets that it received from the GT-482xx for transmission back to port(s) using the
same buffer (without getting an empty buffer). Also the CPU can “take” several empty-buffers (one at a time) write
to them directly, and enqueue them in arbitrary order.
The following registers are used for this process:
CPU_empty_buffer register. This register is loaded by the GT-482xx with the next EL address. The reg-
ister is 32-bits and holds EL address and valid bit. Reading from it signals the GT-482xx that the CPU
owns the buffer (resets valid bit). A new EL request will be issued automatically to the EL block (same
format as before), unless CPU_block_counter register reached the allowed maximum. It is the CPU’s
responsibility to release the buffer (the GT-482xx does not record which buffers are owned by the CPU) -
this is done when the CPU requests enqueueing packet for transmission.
Enqueue_From_CPU register. This 64-bit register is used by the CPU to request enqueueing a packet
to be transmitted over the GT-482xx ports. The CPU writes the End_Of_Packet message here (in the for-
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