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| 型号： | GT-48208 |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高级交换式 10+10/100 BaseX以太网控制器) |
| 中文描述： | 先进的交换式以太网控制器的10 10/100 BaseX（高级交换式10 10/100 BaseX以太网控制器） |
| 文件页数： | 2/135页 |
| 文件大小： | 1619K |
| 代理商： | GT-48208 |
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GT-482xx Switched Ethernet Controllers for 10+10/100 BaseX
GALI
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TECHNOLOGY
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10
Revision 1.2
Port #0 includes five pins (TxEn and Link Status are added) allowing interface to AUI, coax, or fiber-optic media.
1.3
Flow Control and Back Pressure
IEEE standard 802.3x flow control (for full duplex) and proprietary back pressure (for half duplex) are supported on
both the 100Mbps and 10Mbps ports. Back pressure or flow control is activated when the port or device buffer
budget is almost exhausted.
1.4
CPU Interface
The GT-482xx provides a simple interface for low-cost 32-bit bus processors operating at a 16-50Mhz clock rate.
The GT-482xx provides glueless interface to the following processors:
IDT 3041
MIPS 64-bit CPUs (via the Galileo GT-64010A, GT-64011/14 and GT-64120 components)
Motorola ColdFire CPUs (small amount of glue logic required for demuxed bus versions)
Intel i960
Jx and i960Rx
Other CPUs may be attached to the GT-482xx via a PCI bus through the GT-64111 PCI Bridge/Bridge
Memory Controller available from Galileo
In addition, the GT-482xx provides interface to the following processors requiring a minimum amount of glue logic:
80486 and derivatives
i960
Cx and i960Hx processors
PowerPC 401/403 family
The CPU performs management functions such as:
SNMP and RMON
VLAN programming
IP Multicast session initiation
Spanning tree BDPU processing
Packet trapping/transmission/reception
Address table access and query.
Layer 3 routing
NOTE: A CPU is not required in unmanaged GT-482xx configurations.
1.5
Synchronous GRAM/DRAM Interface
The GT-482xx interfaces directly to 1 or 4 Mbytes of synchronous graphics RAM (SGRAM) or standard SDRAM.
The DRAM is used to store the incoming/outgoing packets as well as the Address Table and other device data
structures. The interface to the SGRAM is glueless; all signals needed to control the memory are provided.
The GT-482xx’s SGRAM configurations are:
1 MByte (one 256K x 32 device): Address table contains up to 2K addresses, 512 Rx buffers.
4 Mbyte (two 1Mb x 16 device): Address table contains up to 8K addresses, 2048 Rx buffers.
1.6
Address Recognition
The GT-482xx can recognize up to 8192 (2,024 in 1Mbyte configuration) different Unicast MAC addresses and
unlimited Multicast/Broadcast MAC addresses. An intelligent address recognition mechanism enables filtering and
forwarding packets at full Fast Ethernet wire speed. Hardware address aging and static address support is also
included.
The GT-482xx provides an address self-learning mechanism. Each device has a private AddressTable located in
its DRAM array. As the GT-482xx learns new addresses, it updates the CPU (if present) by sending a
New_Address message.
相关PDF资料 |
PDF描述 |
|---|---|
| GT-48212 | Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高级交换式 10+10/100 BaseX以太网控制器) |
| GT-64010A | System Controller with PCI Interface for R4XXX/ R5000 Family CPUs(带PCI接口用于R4XXX/ R5000 系列 CPUs的系统控制器) |
| GT-64012 | Secondary Cache Controller For the MIPS R4600/4650/4700/5000,(用于MIPS R4600/4650/4700/5000处理器的二级高速缓存控制器) |
| GT-64111 | System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系统控制器) |
| GT-96100A | Advanced Communication Controller That Handles a Wide Range of Serial Communication Protocols,such as Ethernet,Fast Ethernet,and HDLC(通信协议的高级通信协议（以太网、快速以太网、HDLC）控制器) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| GT48212-A6-PBB1C000 | 制造商:Marvell 功能描述: |
| GT48212-A6-PBB-C000 | 制造商:Marvell 功能描述:12 PORT E + 2 PORT FE SWITCH (MANAGED) - Trays |
| GT48300-A1-BBE1C083 | 制造商:Marvell 功能描述:Marvell GT48300-A1-BBE1C083 |
| GT48300-A1-BBE-C000 | 制造商:Marvell 功能描述:Marvell GT48300-A1-BBE-C000 |
| GT48300-A1-BBE-C08 | 制造商:Marvell 功能描述:MVLGT48300-A1-BBE-C083 4 PORT 83MHZ G.LI |
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