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| 型号： | GT-48208 |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高级交换式 10+10/100 BaseX以太网控制器) |
| 中文描述： | 先进的交换式以太网控制器的10 10/100 BaseX（高级交换式10 10/100 BaseX以太网控制器） |
| 文件页数： | 43/135页 |
| 文件大小： | 1619K |
| 代理商： | GT-48208 |
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GT-482xx Switched Ethernet Controllers for 10+10/100 BaseX
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Revision 1.2
15
DQM
I/O
Data output mask: In normal operation, used in read and write cycles to
DRAM. During reset, this pin is sampled by the GT-48212 to indicate the
DRAM size.The GT-482xx always accesses 32-bit values and does not
require a separate DQM for each byte.
DAddr[11:0]
I/O
DRAM Address: In normal operation, Addr lines contains the DRAM
address and bank selection. During reset, pins <11:0> are sampled by the
GT-48212. (See Table 16, “RESET Pin Strapping Options,” on page 66.)
Ras*
I/O
Row Address Strobe: In normal operation, indicates the Row Address.
During reset, this pin in conjunction with Cas* and WE* indicate the CPU
Type. (See Table 19, “CPU Mode Selection,” on page 70.)
Cas*
I/O
Column Address Strobe: In normal operation indicates the Column
Address. During reset, this pin in conjunction with Ras* and WE* indicates
the CPU Type. (See Table 19, “CPU Mode Selection,” on page 70.)
CS*
O
Chip Select: DRAM Chip Select. Indicates the DRAM chip select.
WE*
I/O
Write Enable: In normal operation indicates DRAM write transaction.
During reset, this pin in conjunction with Ras* and Cas* indicates the CPU
Type.
DData[31:0]
also used for configu-
ration parameters
I/O
DRAM Data/GT-482xx parameters: Multiplexed 32-bit SGRAM data bus
and the GT-482xx parameters. In normal operation DData[31:0] connect
directly to the data input/output pins of the SGDRAM devices. During reset,
some of these pins are sampled by the GT-482xx.
10Mbps Interface
TxDE[11:0]
IO
Transmit Data (Ethernet) / Duplex Mode. In normal operation carries the
Transmit Data for the 10Mbps ports. During reset, these pins are sampled by
the GT-482xx to indicate the duplex mode. (See Table 16, “RESET Pin
RxDE[11:0]
I
Receive Data (Ethernet): This pin carries the receive data for the 10Mbps
ports
ColE/GP[11:0]
I
Collision (Ethernet)/General Purpose pins: Collision detect in AUI mode.
In 10Base-T or 10Base-FL these pins are used as general purpose pins.
They are sampled or driven according to the General Purpose register val-
ues.
These pins are GP input pins by default, therefore, in 10BaseT and 10BaseF
modes, these pins should be pulled HIGH or LOW through a 4.7K Ohm
resistor.
TxEn[0]
IO
Transmit Enable: In normal operation indicates that the packet is being
transmitted on port 0.
During reset, this pin is sampled by the GT-482xx to indicate AUI type.
Sclk
I
Serial Clock: 80Mhz clock. This clock is used to recover the receive data
and to generate the transmit clock for the 10Mbps ports.
Table 2:
Pin Functions (Continued)
S ymbol
Ty pe
D escr ip t ion
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PDF描述 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| GT48212-A6-PBB1C000 | 制造商:Marvell 功能描述: |
| GT48212-A6-PBB-C000 | 制造商:Marvell 功能描述:12 PORT E + 2 PORT FE SWITCH (MANAGED) - Trays |
| GT48300-A1-BBE1C083 | 制造商:Marvell 功能描述:Marvell GT48300-A1-BBE1C083 |
| GT48300-A1-BBE-C000 | 制造商:Marvell 功能描述:Marvell GT48300-A1-BBE-C000 |
| GT48300-A1-BBE-C08 | 制造商:Marvell 功能描述:MVLGT48300-A1-BBE-C083 4 PORT 83MHZ G.LI |
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