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型号： GT-48208
厂商： Galileo Technology Services, LLC
英文描述： Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高级交换式 10+10/100 BaseX以太网控制器)
中文描述： 先进的交换式以太网控制器的10 10/100 BaseX（高级交换式10 10/100 BaseX以太网控制器）
文件页数： 40/135页
文件大小： 1619K
代理商： GT-48208
GT-482xx Switched Ethernet Controllers for 10+10/100 BaseX
GALI
LEO
TECHNOLOGY
CONFI
D
ENTI
AL
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DO
NOT
REPRODUCE
134
Revision 1.2
PRELIMINARY
1.2
1/27/99
31. The following changes were made to Table 18, “CPU
Interface Pin Mappings,” on page 70:
- Changed BurstAddr[1:0] in i960Jx to “pull up”
- Changed BurstAddr[1:0] in ColdFire to “pull up”
- Changed RdCEn in ColdFire to “pull up”
- Changed RdCEn in RV32364 to “pull up”
- Header "BurstAddr[1:0]" -> "BurstAddr[2:1]
- Coldfire CPU mode (MCF5202) connected to DA*[0]
32. Section 16.6 "CPU Interface Applications" on page
71, added waveform information
33. Added Section 17.1 "DRAM Configuration" and Sec-
tion 17.2 "DRAM Initialization" on page 80.
34. Table 23, “Global Control, Offset: 0x04,” on page 84,
added that Initial Value should be 0x1 for P-0/1/2 and
0x0 for P-3/4.
35. Table 24, “Status Register, Offset: 0x08,” on page 87,
Initial value [3] is sampled from DQM pin and not
Daddr[5].
36. Table 37, “CPU Enqueue1, Offset: 0x38,” on page 94
added "0-Unicast" for Mult bit function.
37. Table 47 and Table 48 on page 99, changed initial val-
ues.
38. Table 58, “Port Control (10M ports), Offset: 0x400-
0x40C, 0x800 - 0x80C, 0xC00 - 0xC0C,” on
page 102, changed bit 8 field from Reserved to
EaseEn.
39. Table 59, “Port Control 12 (100M ports), Offset:
0x1000,” on page 104, replaced Reserved bit [3:2]
with Priority for Expansion port.
40. Added Table 60, “Port Control 13 (100M ports), Offset:
0x1004,” on page 106Table 72, “CPU Interface Tim-
ings (Tc= 0-70C; Vcc = +3.3V +/- 5%),” on page 122,
corrected min frequency to 1 thd symbol.
41. Table 73, “Switch Engine Interface Timings (Tc= 0-
70C; Vcc = +3.3V +/- 5%),” on page 122, corrected
min frequency as 1 for thd symbol and changed AClk
max frequency to 66MHz.
42. Updated Table 74, “MII, LED and MDC/MDIO Timings
(Tc= 0-70C; Vcc = +3.3V +/- 5%),” on page 123
43. Added Table 75, “Serial Clock Timings (Tc= 0-70C;
Vcc = +3.3V +/- 5%),” on page 124.
44. Added Figure 28: Serial Clock Waveform (SClk) on
page 124
45. Deleted Section 22 "Functional Waveforms", and
included CPU waveform information in Section 16.6
"CPU Interface Applications" on page 71
Table 77: Document History (Continued)
D o cum e nt Ty pe
R e v. #
D at e
C omment s
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