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参数资料
型号： GT-48208
厂商： Galileo Technology Services, LLC
英文描述： Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高级交换式 10+10/100 BaseX以太网控制器)
中文描述： 先进的交换式以太网控制器的10 10/100 BaseX（高级交换式10 10/100 BaseX以太网控制器）
文件页数： 134/135页
文件大小： 1619K
代理商： GT-48208
GT-482xx Switched Ethernet Controllers for 10+10/100 BaseX
GALI
LEO
TECHNOLOGY
CONFI
D
ENTI
AL
--
DO
NOT
REPRODUCE
98
Revision 1.2
1. Note: For compliance with IEEE standards 802.1P and 802.1Q this register should be programmed to 0x8100 for P3/P4.
Table 43: SMI Register, Offset: 0x50
B i t s
Field N a m e
Function
Init i al Va lue
15:0
Data
For SMI READ operation: Two CPU transactions are
required: (1) CPU write to the SMI register with
OpCode = 1, PhyAd, RegAd with the Data being any
value. (2) CPU read from the SMI register. When read-
ing back the SMI register, the Data is the addressed
Phy register contents if the ReadValid bit (#27) is 1.
The Data remains undefined as long as ReadValid is 0.
For SMI WRITE operation: One CPU transaction is
required: CPU write to the SMI register with OpCode =
0, PhyAd, RegAd with the Data to be written to the
addressed Phy register.
N/A
20:16
PhyAd
PHY device address
0x0
25:21
RegAd
PHY device register address
0x0
26
OpCode
0 - Write
1 - Read
0x0
27
ReadValid
1 - indicates that the Read operation has been com-
pleted for the addressed RegAd register, and the data
is valid on the Data field.
0x0
28
Busy
Busy bit
0 - Not Busy, the CPU can re-load this register
1 - Busy - The data in this register was not processed.
The CPU should not re-load this register.
Busy bit is set to 1 by the CPU and cleared when the
data was written to the PHY registers.
0x0
31:29
N/A
This bits should be driven 0x0 during any write to the
SMI register.
0x0
Table 44: 802.1Q Ethertype Register, Offset: 0x54
B i t s
Field N a m e
Funct ion
Init i al Va lu e
15:0
VLEtherType
VL EtherType value
0x0 - P0/P1/P2
0x8100 - P3/P41
Table 45: General Purpose Register1, Offset: 0x58
B i t s
Field N a m e
Funct ion
Initial Va lue
11:0
GP
General Purpose value - These pins are used to sample or
to drive the ColE/GP[11:0] pins in 10Base-T or 10Base-FL
modes.
0x0
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