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参数资料
| 型号： | GT-48208 |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高级交换式 10+10/100 BaseX以太网控制器) |
| 中文描述： | 先进的交换式以太网控制器的10 10/100 BaseX（高级交换式10 10/100 BaseX以太网控制器） |
| 文件页数： | 84/135页 |
| 文件大小： | 1619K |
| 代理商： | GT-48208 |
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GT-482xx Switched Ethernet Controllers for 10+10/100 BaseX
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Revision 1.2
12.4
EASE Interrupts
A status bit indicating the full/empty status of the Ease_Register for each external port supported on the GT-
482xx, is maintained as part of the Interrupt Cause register. When a value is moved from the Ease_Register into
an internal counter or shadow register, a bit is reset in the Interrupt Cause register indicating that the
Ease_Register is now empty. Setting this bit should also generate a processor interrupt. The Interrupt Cause reg-
ister may be read to determine the state of the Ease_Registers, and may be written to clear the interrupt condition
described above. It is possible for the CPU to mask the interrupt condition as well as clear the interrupt condition.
The GT-482xx implements a mask bit in the Interrupt Mask register for each EASE status bit in the Interrupt Cause
register. Masking and clearing the interrupts are executed in a way that is consistent with the other interrupts sup-
ported by the GT-482xx.
12.5
Sampled Packet Indication
Sampled packets are sent to the CPU. The sample indication bits in the descriptor specify which ports on the par-
ticular GT-482xx this sample is associated with. It is possible for a single sample to be associated with more than
one port at a time. For example, a Broadcast packet flooded to all ports may be sampled on several ports if each
of their skip counters had previously been decremented to zero.
Each GT-482xx device operates independently, therefore the CPU can receive the same sample from different
GT-482xx devices. For example, a Broadcast packet flooded to all ports in the system may be sampled by several
GT-482xx’s at the same time. Each sample results in a separate copy of the packet being sent to the CPU. Pack-
ets which would normally be received by the CPU can also be sampled. In this case, only a single copy of the
packet can be sent to the CPU. The CPU is responsible for determining if a sampled packet should be accepted
as a normal receive packet. In the case where a normally received packet is also a sample from multiple the GT-
482xx devices (e.g. a Broadcast packet). The GT-482xx must provide an indication to avoid the CPU from pro-
cessing duplicate packets.
12.6
Error Source Indications
EASE software in the network device must keep track of the last receive error sources and the associated error
conditions. The GT-482xx informs the CPU of error source conditions by sending a New_Address message.
Two types of errors are defined for this procedure: FCS error and frames too long. When the GT-482xx receives a
packet with any of the above conditions, it will send an Error_Source message to the CPU. The Error_Source
message will contain the 48-bit source address of the error packet, the source port number and an indication of
the error type.
12.7
Enabling/Disabling EASE Functionality
An explicit HP EASE enable/disable bit is provided in the Global Control register for the GT-482xx device. When
HP EASE is disabled using this bit, no EASE samples nor Error_Source messages are sent to the CPU. HP EASE
packet sampling can be disabled on a port anytime the internal counter can not be reloaded with a new skip count
because the CPU has not provided any new values via the Ease_Register. Interrupt conditions generated by an
empty Ease_Register can be masked by appropriate bits in the Ease_Full_Mask and/or Interrupt Cause registers.
The following algorithm enables EASE for the first time:
1.
Enable EASE in the Global Control register.
2.
Enable EASE in the Port Control register per port (10Mbit ports - bit [8], 100Mbit ports - bits [3:2] of
PCR12).
3.
Write a skip value to the EASE register of each port.
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