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参数资料
| 型号： | HSP50210JI-52Z |
| 厂商： | Intersil |
| 文件页数： | 26/51页 |
| 文件大小： | 0K |
| 描述： | IC DEMODULATOR COSTAS 84-PLCC |
| 标准包装： | 15 |
| 功能： | 解调器 |
| 频率： | 52MHz |
| RF 型： | AM，FM |
| 封装/外壳： | 84-LCC（J 形引线） |
| 包装： | 管件 |
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HSP50210
PHASE ERROR ACCUMULATOR
FINISHES BEFORE
INTEGRATION COUNTER
SEARCH
INTEGRATION COUNTER
FINISHES BEFORE
PHASE ERROR
ACCUMULATOR
FINISHES BEFORE
INTEGRATION COUNTER
PHASE ERROR ACCUMULATOR
PHASE ERROR
ACCUMULATOR
FINISHES BEFORE
INTEGRATION
COUNTER
INTEGRATION
INTEGRATION
COUNTER FINISHES
BEFORE
PHASE ERROR
ACCUMULATOR
LOCK
COUNTER
FINISHES BEFORE
PHASE ERROR
ACCUMULATOR
AND VERIFY
COUNTER DONE
VERIFY
INTEGRATION COUNTER
FINISHES BEFORE
PHASE ERROR
ACCUMULATOR AND
FALSE
LOCK COUNTER
DONE
FALSE LOCK
ACCUMULATOR
BEFORE
LOCK COUNTER
FALSE
LOCK
FALSE
VERIFY COUNTER
NOT DONE
LOCK COUNTER
NOT DONE
FIGURE 18. ACQUISITION/TRACKING STATE DIAGRAM
Serial Output Controller
The frequency correction terms generated by the Symbol
and Carrier Loop Filters are output through two separate
serial interfaces. The symbol frequency offset used to close
the symbol Tracking Loop is output via the SOF and
CLK/
SLOCLK
COFSYNC/
SOFSYNC
SOFSYNC outputs. The carrier offset frequency used to
close the Carrier Tracking Loop is output via the COF and
COF/
SOF
MSB
MSB
COFSYNC outputs.
The serial output timing, identical for both of the loop filter
outputs, is shown in Figure 19. The data word is output MSB
first starting with the first rising edge of either CLK or
SLOCLK that follows the assertion of sync (COFSYNC or
SOFSYNC). The HSP50210 is configured to output the
serial data with either CLK or SLOCLK (see Serial Output
Configuration Control Registers Bit 7, Table 42 on page 42).
The SLOCLK output is a programmable sub-multiple of CLK
which is provided for applications requiring a slower serial
clock. In applications where the HSP50210 is used with the
HSP50110, both parts must be supplied with the same CLK
and the HSP50210 is configured to use CLK as the serial
clock. The serial output can be configured for word
containing from 8 to 40 bits.
26
Note: COFSYNC and SOFSYNC shown Configured as
active “High”.
FIGURE 19. SERIAL OUTPUT TIMING FOR COF AND SOF
OUTPUTS
Output Selector
The output selector determines which internal signals are
multiplexed to the AOUT9-0 and BOUT9-0 outputs. Fifteen
different output options are provided: ISOFT(2:0), QSOFT(2:0),
IEND(7:1), QEND(7:1), AGC(7:1), MAG(7:0), Phase(7:0),
FREQERR(7:1), GAINERR(7:1), BITPHERR(7:1),
CARPHERR(7:1), LKACC(6:0), LKCNT(6:0), NCOCOS(9:0),
and STATUS (6:0). These are detailed in the Output Selector
Configuration Control Register, bits 0 through3 (see Table 43
on page 44).
FN3652.5
July 2, 2008
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相关代理商/技术参数 |
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| HSP50214 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Programmable Downconverter |
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| HSP50214AVC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50214AVI | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Programmable Downconverter |
| HSP50214B | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Programmable Downconverter |
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