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| 型号： | HSP50210JI-52Z |
| 厂商： | Intersil |
| 文件页数： | 44/51页 |
| 文件大小： | 0K |
| 描述： | IC DEMODULATOR COSTAS 84-PLCC |
| 标准包装： | 15 |
| 功能： | 解调器 |
| 频率： | 52MHz |
| RF 型： | AM，FM |
| 封装/外壳： | 84-LCC（J 形引线） |
| 包装： | 管件 |
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HSP50210
:
TABLE 43. OUTPUT SELECTOR CONFIGURATION CONTROL REGISTER
DESTINATION ADDRESS = 28
BIT POSITION
31-8
7-4
3-0
FUNCTION
Not Used
Reserved
Output Select
44
DESCRIPTION
No programming required.
Set to zero for proper operation.
These bits select which input signals are routed to the 20 output pins AOUT9-0 and BOUT9-0. The signal
selections are listed below in Tables 43A and 43B.
Definition of Signal Bus Names
DATA SIGNAL BUSSES
ISOFT(2:0)
This bus is the I channel soft decision slicer output data, expressed in the data format set
by CW26 bit 7, with one sign bit (ISOFT2) and two soft decision bits.
QSOFT(2:0) This bus is the Q channel soft decision slicer output data, expressed in the data format set
by CW26 bit 7, with one sign bit (QSOFT2) and two soft decision bits.
IEND(7:1) This bus is the 7 MSBs of I end symbol sample into the soft decision slicer, in 2’s
complement format. (MSB = Iend7).
QEND(7:1) This bus is the 7 MSBs of Q end symbol sample into the soft decision slicer, in 2’s
complement format. (MSB = Qend7).
STATUS SIGNAL PARAMETER BUSSES
AGC(7:1) . . . . . .This bus is the 7 MSBs of the AGC Accumulator Register. (MSB = AGC7).
MAG (7:0) . . . . .This bus is the 8-bit magnitude output of the Cartesian to Polar converter, in unsigned
binary format. (MSB = MAG7).
PHASE (7:0) . . .This bus is the 8-bit phase output of the Cartesian to Polar converter, in unsigned binary
format. (MSB = PHASE7).
FE(7:1) . . . . . . .This bus is the seven MSBs of the Frequency Error Detector Output Register, in 2’s
complement format. (MSB = FE7).
GE (7:1) . . . . . .This bus is the seven MSBs of the Gain Error (AGC) Accumulator Register, in 2’s
complement format. (MSB = GE7).
TE (7:1) . . . . . .This bus is the seven MSBs of the Bit Phase Error Detector Output Register, in 2’s
complement format. (MSB = TE7).
CARPE (7:1) . . .This bus is the seven MSBs of the Carrier Phase Error Detector Output Register, in 2’s
complement format. (MSB = PE7).
LKACC(6:0) . . .This bus is the seven LSBs of the Phase Error Accumulator Register in the Lock Detector,
in unsigned offset binary format. (MSB = LKACC6) If accumulation Bits 14-17 = 1, then
Bits 7-13 are output as LKACC(6.0). These outputs are zero otherwise.
LKCNT(6:0) . . .This bus is the seven LSBs of the Integration Counter in the Lock Detector, in one’s
complement format. (MSB = LKCNT6) If Bits 7-9 of the accumulator are zero, then Bits
0-6 are output as LKCNT(6-0). These outputs are zero otherwise.
NCOCOS(9:0) . .This bus is the 10-bit two’s complement output of the DCL NCO, in 2’s complement
format. (MSB = NCOCOS7).
Applications for the Various Output Signals
ISOFT(2:0) and QSOFT(2:0)
These signals provide a simple interface to a FEC decoder. As the most likely to be used output bus, these
signals are included in all but one of the programmable multiplexer output configurations.
IEND(7:1) and QEND(7:1)
These signals are useful when input to a D/A converter and displayed on an oscilloscope in the X-Y plot.
This will yield the constellation signal display with which analog modem designers are familiar.
STATUS(6:0)
These signals can be used in fault detection for use in BIT/BITE applications and are useful during system
debug .
AGC(7:1)
This signal is useful in monitoring the AGC operation, signal detection and antenna tracking applications.
Other single bit signals are provided for direct use in external AGC.
MAG(7:0) and PHASE(7:0)
These signals are useful in signal detection applications, where presence of a signal is represented by a
particular signal magnitude or phase.
FN3652.5
July 2, 2008
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相关代理商/技术参数 |
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| HSP50214 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Programmable Downconverter |
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| HSP50214B | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Programmable Downconverter |
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