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参数资料
| 型号： | HSP50210JI-52Z |
| 厂商： | Intersil |
| 文件页数： | 30/51页 |
| 文件大小： | 0K |
| 描述： | IC DEMODULATOR COSTAS 84-PLCC |
| 标准包装： | 15 |
| 功能： | 解调器 |
| 频率： | 52MHz |
| RF 型： | AM，FM |
| 封装/外壳： | 84-LCC（J 形引线） |
| 包装： | 管件 |
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HSP50210
WR
RD
A0-2
4
5
4
3
2
1
0
4
C0-7
24
3
30
25
SR7=0
SR7=1
PE MSW
PE LSW
FL MSW
FL LSW
CLK
SR-7
1
2
3 4
5
6 7
8
6
8
6
8
6
8
9
10
HALT LD
AT END OF
CYCLE
ENABLE INTERNAL
LD REG. STATUS READS
FOR READING
LOCK DETECTION STATUS READS
RESET RESTART
LOCK LOCK
DETECTOR DETECTOR
NOTE: These processor signals are meant to be representative. The actual shape of the waveforms will be set by the microprocessor used. Verify
that the processor waveforms meet the parameters in “Waveforms” on page 50 to ensure proper operation. The Processor waveforms are not
required to be synchronous to CLK. They are shown that way to clarify the illustration.
1. Load the Write Address Register with 24 dec to halt the Lock Detector after the current integration cycle. This disables the reload of the integration
counter in the lock detector. The verify counter is not reset and will resume at the stopped value when the lock detector is restarted.
2. Load the Read Address Register with 3 dec to enable the Lock Detector Phase Error Accumulator for reading.
3. Read Internal Status Register to monitor SR-7 to determine when the Lock Detector is stopped and ready to be read.
4. SR-7 goes high, indicating the Lock Detector integration cycle is complete, and ready to be read.
5. Read Internal Status Register and find SR-7 = 1; the Lock Detector is ready to be read.
6. Change Read address to (3; 2; 1; 0) for (Phase Error MSW; PE LSW; False Lock MSW; FL LSW) read.
7. End of Internal Status Valid Data.
8. Assert RD to Read Lock Detector Status
9. Load The Write Address Register with 30 dec to initialize Lock Detector Accumulators and Reset the Integration counters. (Not needed for state
machine mode).
10. Load the Write Address Register with 25 dec to restart the Lock Detector.
FIGURE 23. PROCESSOR MONITORING INTERNAL STATUS/READING LOCK DETECTOR
TABLE 14. INTERNAL STATUS REGISTER (SR7-0) BIT MAP
BIT
7
6
5
BIT DESCRIPTION
Lock Detector Stopped and Ready for Reading
(State Machine Control Mode).
0 = Lock Detector not stopped.
1 = Lock Detector stopped, ready for read.
Lock Detector Stopped and Ready for Reading
(Microprocessor Control Mode).
0 = Lock Detector not stopped.
1 = Lock Detector stopped, ready for read.
Carrier Loop Filter Lag Accumulator Load Complete. This bit
is used to determine when a 32-bit load of Carrier Lag
Accumulator is complete. The accumulator load is initialized
by loading the Write Address Register with 13 (decimal) as
described in Table 28.
BIT
3
2
1
0
BIT DESCRIPTION (Continued)
Lock. Carrier Lock state achieved by Lock Detector.
0 = Not locked.
1 = Locked.
Acquisition/Track. Indicates whether the Lock Detector is in
acquisition or tracking mode.
0 = Tracking Mode.
1 = Acquisition Mode.
Reserved.
Frequency Sweep Direction, defined for upper sideband
signals.
0 = UP.
1 = DOWN.
0 = Load not complete.
1 = Load complete.
4
Symbol Tracking Loop Filter Lag Accumulator Load
Complete. This bit is used to determine when a 32-bit load of
Symbol Track Lag Accumulator is complete. The
accumulator load is initialized by loading the Write Address
Register with 19 (decimal) as described in Table 34.
0 = Load not complete.
1 = Load complete.
30
FN3652.5
July 2, 2008
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