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| 型号： | HSP50210JI-52Z |
| 厂商： | Intersil |
| 文件页数： | 43/51页 |
| 文件大小： | 0K |
| 描述： | IC DEMODULATOR COSTAS 84-PLCC |
| 标准包装： | 15 |
| 功能： | 解调器 |
| 频率： | 52MHz |
| RF 型： | AM，FM |
| 封装/外壳： | 84-LCC（J 形引线） |
| 包装： | 管件 |
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HSP50210
TABLE 42. SERIAL OUTPUT CONFIGURATION CONTROL REGISTER (Continued)
DESTINATION ADDRESS = 27
BIT
POSITION
10
9-8
7
6-4
3
2-0
FUNCTION
Serial Clock Phase
Relative to Data
Serial Clock Divider
Serial Clock Select for
COF Output
Serial Word Length for
COF Output
Serial Clock Select for
SOF Output
Serial Word Length for
SOF Output
43
DESCRIPTION
0 = Rising edge of serial clock at center of data bit.
1 = Falling edge of serial clock at center of data bit. Set to 0 for use with the HSP50110.
These bits set the clock rate of SLOCLK.
00 -> SLOCLK = CLK/2.
01 -> SLOCLK = CLK/4.
10 -> SLOCLK = CLK/8.
11 -> SLOCLK = CLK/16.
0 = CLK is used as the serial clock.
1 = SLOCLK is used as the serial clock.
Note: If the HSP50210 is used together with the HSP50110, CLK must be selected as the serial clock for
the SOF and COF outputs, and the same CLK must be used by both chips.
000 = 8 Bits
001 = 12 Bits
010 = 16 Bits
011 = 20 Bits
100 = 24 Bits
101 = 28 Bits
110 = 32 Bits
111 = 40 Bits
0 = CLK is used as the serial clock.
1 = SLOCLK is used as the serial clock.
Note: If the HSP50210 is used together with the HSP50110, CLK must be selected as the serial clock for
the SOF and COF outputs, and the same CLK must be used by both chips.
000 = 8 Bits
001 = 12 Bits
010 = 16 Bits
011 = 20 Bits
100 = 24 Bits
101 = 28 Bits
110 = 32 Bits
111 = 40 Bits
FN3652.5
July 2, 2008
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